Lab II
Lab II
Lab II
Integrated Circuits
Lab II Characterizing and Sizing I
Geovanny Satama 00138700
Introduction
George Boole fue un matemático y filosofo que propuso la idea de que muchos de los fenómenos
del universo se pueden expresar a través de la lógica proposicional, cual dio paso a que se
desarrolle el algebra booleana, cual en conjunto de las variables binarias se logró generar la lógica
binaria, cual consta de compuertas lógicas como son; “AND”, “NOT”, “OR” y entre otras con las
que se logra analizar y realizar secuencias específicas. Actualmente en la electrónica se juntas estas
compuertas lógicas con transistores para poder llevar a acabo operaciones como; la suma, resta,
multiplicación y otras mas que se presentan continuamente en la industria, permitiendo controlar
procesos específicos y tener una trazabilidad de las operaciones que se realizan en el mismo; en
esta práctica se realizaron distintos diseños de compuertas para variar el largo y ancho de los
MOSFET. Se toma la premisa de que el Width de los Pmos debe ser mayor que del nmos, ya que
se presentan huecos mas lentos que los electrones, recomendándose que el tamaño del pmos sea
𝑤𝑤𝑝𝑝
aproximadamente el doble que del nmos, cual se rige por la ecuación 𝑤𝑤 = 2.
𝑛𝑛
Procedure
The width of the mosfets was determined in different configurations, while the length that was
used was 90nm. When performing the simulation, a DC sweep is used to see the voltage transfer
curve, where it was sought that the current line intersects with the voltage curve where it is VIN /
2.
For the calculation of the factor ∝𝑠𝑠 , also known as Alpha stack, the following formula was used:
𝑊𝑊 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑒𝑒𝑑𝑑
𝛼𝛼𝑠𝑠 =
𝑊𝑊 know
Where the W know comes out of the value that we get from the investor.
For the noise margin we consider the following graph from (Takbiri, Mirzaee, & Navi, 2019):
Where we will call the first slope point 1 and for the second, which is seen at the bottom, we will
call it point 2.
The following formulas were used:
𝑁𝑁𝑀𝑀𝐻𝐻 = 𝑉𝑉𝑂𝑂𝑂𝑂 − 𝑉𝑉𝐼𝐼𝐼𝐼
𝑁𝑁𝑀𝑀𝐿𝐿 = 𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂
Inversor
Schematic
The inverter was designed as follows:
Sizing
To determine the size of one of the two mosfets, we leave a fixed size, for this we define the size
of type n as 0.5 um.
The inverter was implemented to carry out the testbench, as follows:
Where
𝑉𝑉𝑂𝑂𝑂𝑂 = 1.03𝑉𝑉
𝑉𝑉𝐼𝐼𝐼𝐼 = 521 𝑚𝑚𝑉𝑉
While for point 2 the following was obtained:
Where:
𝑉𝑉𝑂𝑂𝑂𝑂 = 120 𝑚𝑚𝑚𝑚
𝑉𝑉𝐼𝐼𝐼𝐼 = 681 𝑚𝑚𝑚𝑚
Then:
𝑁𝑁𝑀𝑀𝐻𝐻 = 1.03 − 681𝑚𝑚 = 349 𝑚𝑚𝑚𝑚
𝑁𝑁𝑀𝑀𝐿𝐿 = 521𝑚𝑚 − 120𝑚𝑚 = 401 𝑚𝑚𝑚𝑚
2-input NOR
Schematic
The 2-input NOR was designed as follows:
Sizing
The fixed size remains in 𝑊𝑊n , which is the one that is not stacked, while we vary the size of 𝑊𝑊p .
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Then comparing what is obtained in the graph with the table we conclude that the gate works
satisfactorily.
Alpha stack
To calculate it we use the following formula:
𝑊𝑊𝑝𝑝 0.57𝑢𝑢
𝛼𝛼𝑠𝑠 = = = 2.47
𝑊𝑊𝑛𝑛 0.23𝑢𝑢
Noise margin (High and low)
The points were chosen at the same distance from the center, where the curvature with a tendency
to a slope of -1 is graphically appreciated.
For the first point it was obtained:
Where
𝑉𝑉𝑂𝑂𝑂𝑂 = 899 𝑚𝑚𝑚𝑚
𝑉𝑉𝐼𝐼𝐼𝐼 = 557 𝑚𝑚𝑉𝑉
While for point 2 the following was obtained:
Where
𝑉𝑉𝑂𝑂𝑂𝑂 = 155 𝑚𝑚𝑚𝑚
𝑉𝑉𝐼𝐼𝐼𝐼 = 643 𝑚𝑚𝑚𝑚
Then:
𝑁𝑁𝑀𝑀𝐻𝐻 = 899𝑚𝑚 − 643𝑚𝑚 = 256 𝑚𝑚𝑚𝑚
𝑁𝑁𝑀𝑀𝐿𝐿 = 557𝑚𝑚 − 155𝑚𝑚 = 402 𝑚𝑚𝑚𝑚
2-input NAND
Schematic
The 2-input NAND was designed as follows
Sizing
The fixed size remains in 𝑊𝑊𝑝𝑝 which is the one that is not stacked, while we vary the size of 𝑊𝑊n .
The 2-input NAND was implemented to perform the testbench, as follows:
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Then, comparing what is obtained in the graph, it is concluded that it works correctly.
Alpha stack
To calculate it we use the following formula:
𝑊𝑊𝑛𝑛 0.32𝑢𝑢
𝛼𝛼𝑠𝑠 = = = 0.06
𝑊𝑊𝑝𝑝 0.5𝑢𝑢
Where
𝑉𝑉𝑂𝑂𝑂𝑂 = 973 𝑚𝑚𝑚𝑚
𝑉𝑉𝐼𝐼𝐼𝐼 = 550 𝑚𝑚𝑚𝑚
While for point 2 the following was obtained:
Where
𝑉𝑉𝑂𝑂𝑂𝑂 = 181 𝑚𝑚𝑚𝑚
𝑉𝑉𝐼𝐼𝐼𝐼 = 650 𝑚𝑚𝑚𝑚
Then:
𝑁𝑁𝑀𝑀𝐻𝐻 = 973𝑚𝑚 − 650𝑚𝑚 = 323 𝑚𝑚𝑚𝑚
𝑁𝑁𝑀𝑀𝐿𝐿 = 550𝑚𝑚 − 181𝑚𝑚 = 369 𝑚𝑚𝑚𝑚
Conclusion
When the mosfets for the different gates are stacked, a sizing of the stack gate must be done, since
in this way there is a mosfet whose voltage curves coincide with the midpoint of the voltage, with
which the gate works correctly and the vout matches what it should come out with respect to the
truth table.
At the time of sizing, in the testbench, the sources that enter the gate can be Vpulse or Vdc. Vdc
is enough because when performing the DCsweep the input voltage is already varied and with this
the “voltage transfer curve” is obtained. However, having a Vpulse from before serves so that
when checking the operation the sources should not be changed.
However, when making the NAND gate, it started with Vdc sources because due to some error the
“voltage transfer curve” did not appear, then when using Vdc sources it already came out and it
could be sized. Then to check the operation if you had to switch to Vpulse sources.
Bibliography
Takbiri, M., Mirzaee, R. F., & Navi, K. (2019, February 22). Analytical Review of Noise Margin
in MVL: Clarification of a Deceptive Matter. Retrieved from
https://link.springer.com/article/10.1007/s00034-019-01063-8