@@ -103,7 +103,7 @@ performed before the barrier, and vice-versa.
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Although this code will work, it is needlessly inefficient. On systems with
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strong memory ordering (such as x86), the CPU never reorders loads with other
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- loads, nor stores with other stores. It can, however, allow a load to
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+ loads, nor stores with other stores. It can, however, allow a load to be
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performed before a subsequent store. To avoid emitting unnecessary memory
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instructions, we provide two additional primitives: pg_read_barrier(), and
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pg_write_barrier(). When a memory barrier is being used to separate two
@@ -155,18 +155,16 @@ Although this may compile down to a single machine-language instruction,
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the CPU will execute that instruction by reading the current value of foo,
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adding one to it, and then storing the result back to the original address.
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If two CPUs try to do this simultaneously, both may do their reads before
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- either one does their writes. Eventually we might be able to use an atomic
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- fetch-and-add instruction for this specific case on architectures that support
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- it, but we can't rely on that being available everywhere, and we currently
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- have no support for it at all. Use a lock.
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+ either one does their writes. Such a case could be made safe by using an
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+ atomic variable and an atomic add. See port/atomics.h.
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2. Eight-byte loads and stores aren't necessarily atomic. We assume in
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various places in the source code that an aligned four-byte load or store is
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atomic, and that other processes therefore won't see a half-set value.
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Sadly, the same can't be said for eight-byte value: on some platforms, an
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aligned eight-byte load or store will generate two four-byte operations. If
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- you need an atomic eight-byte read or write, you must make it atomic with a
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- lock.
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+ you need an atomic eight-byte read or write, you must either serialize access
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+ with a lock or use an atomic variable .
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3. No ordering guarantees. While memory barriers ensure that any given
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process performs loads and stores to shared memory in order, they don't
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