@@ -78,10 +78,9 @@ typedef struct pg_atomic_uint64
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} pg_atomic_uint64 ;
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#endif
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- #endif /* defined(HAVE_ATOMICS) */
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+ #endif /* defined(HAVE_ATOMICS) */
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- #endif /* defined(__GNUC__) &&
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- * !defined(__INTEL_COMPILER) */
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+ #endif /* defined(__GNUC__) && !defined(__INTEL_COMPILER) */
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#if defined(PG_USE_INLINE ) || defined(ATOMICS_INCLUDE_DEFINITIONS )
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@@ -94,20 +93,20 @@ typedef struct pg_atomic_uint64
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* PAUSE in the inner loop of a spin lock is necessary for good
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* performance:
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*
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- * The PAUSE instruction improves the performance of IA-32
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- * processors supporting Hyper-Threading Technology when
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- * executing spin-wait loops and other routines where one
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- * thread is accessing a shared lock or semaphore in a tight
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- * polling loop. When executing a spin-wait loop, the
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- * processor can suffer a severe performance penalty when
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- * exiting the loop because it detects a possible memory order
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- * violation and flushes the core processor's pipeline. The
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- * PAUSE instruction provides a hint to the processor that the
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- * code sequence is a spin-wait loop. The processor uses this
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- * hint to avoid the memory order violation and prevent the
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- * pipeline flush. In addition, the PAUSE instruction
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- * de-pipelines the spin-wait loop to prevent it from
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- * consuming execution resources excessively.
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+ * The PAUSE instruction improves the performance of IA-32
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+ * processors supporting Hyper-Threading Technology when
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+ * executing spin-wait loops and other routines where one
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+ * thread is accessing a shared lock or semaphore in a tight
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+ * polling loop. When executing a spin-wait loop, the
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+ * processor can suffer a severe performance penalty when
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+ * exiting the loop because it detects a possible memory order
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+ * violation and flushes the core processor's pipeline. The
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+ * PAUSE instruction provides a hint to the processor that the
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+ * code sequence is a spin-wait loop. The processor uses this
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+ * hint to avoid the memory order violation and prevent the
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+ * pipeline flush. In addition, the PAUSE instruction
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+ * de-pipelines the spin-wait loop to prevent it from
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+ * consuming execution resources excessively.
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*/
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#if defined(__INTEL_COMPILER )
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#define PG_HAVE_SPIN_DELAY
@@ -121,8 +120,8 @@ pg_spin_delay_impl(void)
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static __inline__ void
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pg_spin_delay_impl (void )
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{
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- __asm__ __volatile__(
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- " rep; nop \n" );
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+ __asm__ __volatile__(
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+ " rep; nop \n" );
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}
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#elif defined(WIN32_ONLY_COMPILER ) && defined(__x86_64__ )
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#define PG_HAVE_SPIN_DELAY
@@ -137,10 +136,10 @@ static __forceinline void
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pg_spin_delay_impl (void )
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{
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/* See comment for gcc code. Same code, MASM syntax */
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- __asm rep nop ;
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+ __asm rep nop ;
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}
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#endif
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- #endif /* !defined(PG_HAVE_SPIN_DELAY) */
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+ #endif /* !defined(PG_HAVE_SPIN_DELAY) */
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#if defined(HAVE_ATOMICS )
@@ -154,13 +153,12 @@ pg_atomic_test_set_flag_impl(volatile pg_atomic_flag *ptr)
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{
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register char _res = 1 ;
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- __asm__ __volatile__(
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- " lock \n"
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- " xchgb %0,%1 \n"
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- : "+q" (_res ), "+m" (ptr -> value )
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- :
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- : "memory" );
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-
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+ __asm__ __volatile__(
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+ " lock \n"
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+ " xchgb %0,%1 \n"
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+ : "+q" (_res ), "+m" (ptr -> value )
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+ :
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+ : "memory" );
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return _res == 0 ;
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}
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@@ -172,8 +170,7 @@ pg_atomic_clear_flag_impl(volatile pg_atomic_flag *ptr)
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* On a TSO architecture like x86 it's sufficient to use a compiler
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* barrier to achieve release semantics.
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*/
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- __asm__ __volatile__("" :::"memory" );
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-
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+ __asm__ __volatile__("" ::: "memory" );
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ptr -> value = 0 ;
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}
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@@ -182,35 +179,33 @@ static inline bool
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pg_atomic_compare_exchange_u32_impl (volatile pg_atomic_uint32 * ptr ,
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uint32 * expected , uint32 newval )
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{
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- char ret ;
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+ char ret ;
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/*
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* Perform cmpxchg and use the zero flag which it implicitly sets when
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* equal to measure the success.
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*/
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- __asm__ __volatile__(
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- " lock \n"
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- " cmpxchgl %4,%5 \n"
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- " setz %2 \n"
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- : "=a" (* expected ), "=m" (ptr -> value ), "=q" (ret )
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- : "a" (* expected ), "r" (newval ), "m" (ptr -> value )
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- : "memory" , "cc" );
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-
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+ __asm__ __volatile__(
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+ " lock \n"
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+ " cmpxchgl %4,%5 \n"
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+ " setz %2 \n"
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+ : "=a" (* expected ), "=m" (ptr -> value ), "=q" (ret )
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+ : "a" (* expected ), "r" (newval ), "m" (ptr -> value )
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+ : "memory" , "cc" );
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return (bool ) ret ;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U32
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static inline uint32
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pg_atomic_fetch_add_u32_impl (volatile pg_atomic_uint32 * ptr , int32 add_ )
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{
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- uint32 res ;
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- __asm__ __volatile__(
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- " lock \n"
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- " xaddl %0,%1 \n"
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- : "=q" (res ), "=m" (ptr -> value )
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- : "0" (add_ ), "m" (ptr -> value )
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- : "memory" , "cc" );
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-
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+ uint32 res ;
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+ __asm__ __volatile__(
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+ " lock \n"
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+ " xaddl %0,%1 \n"
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+ : "=q" (res ), "=m" (ptr -> value )
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+ : "0" (add_ ), "m" (ptr -> value )
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+ : "memory" , "cc" );
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return res ;
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}
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@@ -221,44 +216,40 @@ static inline bool
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pg_atomic_compare_exchange_u64_impl (volatile pg_atomic_uint64 * ptr ,
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uint64 * expected , uint64 newval )
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{
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- char ret ;
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+ char ret ;
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/*
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* Perform cmpxchg and use the zero flag which it implicitly sets when
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* equal to measure the success.
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*/
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- __asm__ __volatile__(
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- " lock \n"
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- " cmpxchgq %4,%5 \n"
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- " setz %2 \n"
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- : "=a" (* expected ), "=m" (ptr -> value ), "=q" (ret )
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- : "a" (* expected ), "r" (newval ), "m" (ptr -> value )
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- : "memory" , "cc" );
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-
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+ __asm__ __volatile__(
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+ " lock \n"
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+ " cmpxchgq %4,%5 \n"
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+ " setz %2 \n"
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+ : "=a" (* expected ), "=m" (ptr -> value ), "=q" (ret )
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+ : "a" (* expected ), "r" (newval ), "m" (ptr -> value )
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+ : "memory" , "cc" );
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return (bool ) ret ;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U64
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static inline uint64
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pg_atomic_fetch_add_u64_impl (volatile pg_atomic_uint64 * ptr , int64 add_ )
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{
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- uint64 res ;
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- __asm__ __volatile__(
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- " lock \n"
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- " xaddq %0,%1 \n"
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- : "=q" (res ), "=m" (ptr -> value )
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- : "0" (add_ ), "m" (ptr -> value )
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- : "memory" , "cc" );
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-
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+ uint64 res ;
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+ __asm__ __volatile__(
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+ " lock \n"
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+ " xaddq %0,%1 \n"
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+ : "=q" (res ), "=m" (ptr -> value )
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+ : "0" (add_ ), "m" (ptr -> value )
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+ : "memory" , "cc" );
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return res ;
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}
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- #endif /* __x86_64__ */
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+ #endif /* __x86_64__ */
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- #endif /* defined(__GNUC__) &&
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- * !defined(__INTEL_COMPILER) */
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+ #endif /* defined(__GNUC__) && !defined(__INTEL_COMPILER) */
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- #endif /* HAVE_ATOMICS */
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+ #endif /* HAVE_ATOMICS */
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- #endif /* defined(PG_USE_INLINE) ||
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- * defined(ATOMICS_INCLUDE_DEFINITIONS) */
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+ #endif /* defined(PG_USE_INLINE) || defined(ATOMICS_INCLUDE_DEFINITIONS) */
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