axi
Here are 73 public repositories matching this topic...
🏄 Custom IP for vector operations
-
Updated
Aug 31, 2024 - VHDL
-
Updated
Sep 16, 2023 - JavaScript
Spotify Clone With Reactjs
-
Updated
Jan 2, 2022 - JavaScript
FPGA interface and driver for an OV7670 camera sensor.
-
Updated
Aug 28, 2023 - VHDL
Реализация AXI интерфейса на SystemVerilog
-
Updated
Jul 25, 2024 - SystemVerilog
The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure
-
Updated
Nov 24, 2023 - C
Сервис по подбору доступного жилья.
-
Updated
Sep 16, 2023 - JavaScript
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
-
Updated
May 1, 2020 - Tcl
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
-
Updated
Apr 13, 2024 - VHDL
Improve this page
Add a description, image, and links to the axi topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi topic, visit your repo's landing page and select "manage topics."