Abstract—This paper proposes a scalable neuromorphic pro- cessor utilizing asynchronous routers and configurable LIF neu- ron models.
... Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron ... Energy Efficient 0.5V 4.8pJ/SOP 0.93µW Leakage/Core Neuromorphic ...
Abstract—This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves ...
Paper Information: Paper Title: 0.5V 4.8 pJ/SOP 0.93µW Leakage/Core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.
This repo collects papers, docs, codes about neuromorphic hardware for anyone who wants to do research on it. We are continuously improving the project.
0.5 V 4.8 pJ/SOP 0.93\mu\mathrm {W} $ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. VP Nambiar, J Pu, YK Lee, A Mani, ...
Energy Efficient 0.5V 4.8pJ/SOP 0.93µW Leakage/Core Neuromorphic Processor Design ... neuromorphic processor with asynchronous routers and configurable LIF neuron ...
Jul 23, 2024 · 0.5V 4.8 pJ/SOP 0.93μW Leakage/core neuromorphic processor with asynchronous NoC and reconfigurable LIF neuron. In 2020 IEEE Asian Solid ...
An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper and a ...
