This paper describes a background digital calibration technique based on bitwise correlation (BWC) to correct the capacitive digital-to-analog converter ...
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Abstract—This paper describes a background digital calibration technique based on bitwise correlation (BWC) to correct the capacitive digital-to-analog ...
This paper describes a 12-bit sub-radix-2 SAR ADC with perturbation-based digital calibration employing four different comparator designs to optimize power ...
Apr 25, 2024 · A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight ... A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration.
A redundant double conversion (RDC) based digital background technique for successive approximation analogue-to-digital converters (SAR ADCs) with ...
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. T. Morie. A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing ...
A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed.
Liu et al., A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration, in Proc. CICC, Sept. 2012, pp. 1-4. [12] Y. Chiu et al., An ICA framework ...
Nov 5, 2020 · This paper presents a switched capacitive reference driver (SCRD) with a low-energy switching scheme. In order to reduce the performance ...
Dec 3, 2014 · Chiu, "A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration," in CICC,. 2012. 19. W. Liu, P. Huang, and Y. Chiu, "A 12bit 22.5 ...