A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval ...

An SNN circuit that utilizes resource-sharing techniques to address the two challenges of fully-parallel high-throughput synapse connections and a ...

In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12- ...

... A CMOS Axon-sharing Neuron Array with Background Calibration. Xiangao Qi 1. ,. Jian Zhao 1. ,. Wang GuoXing 1. ,. Kea Tiong Tang 2. ,. Yongfu Li 1. Show full ...

This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain ...

Firstly, a comparator sharing neuron circuit with a background calibration technique is proposed to shrink the size of a single neuron without performance ...

Dec 9, 2024 · Firstly, a comparator sharing neuron circuit with a background calibration technique is proposed to shrink the size of a single neuron without ...

A 5.3 pJ/Spike CMOS Neural Array Employing Time-Modulated Axon-Sharing and Background Mismatch Calibration Techniques · Figures and Tables · Topics · 2 Citations ...

Firstly, a comparator sharing neuron circuit with a background calibration ... Secondly, a time-modulated axon-sharing synapse ... To validate the proposed ...

... Array Employing Time-Modulated Axon-Sharing and Background Mismatch Calibration Techniques. ... A CMOS Axon-sharing Neuron Array with Background Calibration.ISCAS ...