In this paper, we develop a SAT solver based on the hardware FPGA. In the solver, an improved DPLL algorithm is embedded in FPGA to solve satisfiable problems.
Abstract—Various types of SAT solvers are widely used in model checking for ensuring the reliability of software and hardware systems.
A FPGA Based SAT Solver with High Random and Concurrent ...
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In the solver, an improved DPLL algorithm is embedded in FPGA to solve satisfiable problems and the experimental results show that this solver is an ...
A randomized simulation is called time-processor optimal if the delay is O(m=n) with high probability. Using a novel simulation scheme based on hashing we ...
Apr 13, 2024 · We present a hardware-accelerated SAT solver targeting processor/Field Programmable Gate Arrays (FPGA) SoCs. Our solution accelerates the ...
Nov 1, 2021 · In this work, a parallel multi-thread SAT solver on an FPGA is proposed. In the algorithm, three independent threads are executed at the same ...
Missing: Concurrent | Show results with:Concurrent
Jan 15, 2024 · Li, and J. Wu, “A fpga based sat solver with high random and concurrent strategies,” in 2018 IEEE International Conference on Software Quality, ...
A hardware analyzer for the Boolean satisfiability problem using a complete algorithm was developed for an Alter a DE2-70 Cyclone II FPGA board.
This article proposes an approach for solving large 3-SAT problems on FPGA using a WSAT algorithm, and can solve larger problems than previous works with ...
Jun 12, 2024 · We present a hardware-accelerated SAT solver targeting processor/Field Programmable Gate Arrays (FPGA) SoCs. Our solution accelerates the ...