In this paper, a highly linear DCDL with reduced duty cycle distortion is proposed and designed in a 28nm CMOS process. By incorporating both PMOSCAPs and ...
duty cycle distortion. Designed and simulated in a 28nm. CMOS process, the amount of duty cycle distortion is reduced to maximum of 5.7%, which is 7.7 times ...
The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low ...
In this paper, a highly linear DCDL with reduced duty cycle distortion is proposed and designed in a 28nm CMOS process. By incorporating both PMOSCAPs and ...
Delay lines adjust the edge locations of the data or strobe such that strobe is centre aligned with respect to data. This improves the timing margins and ...
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In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line ...
An alternative digital delay line is a cycle controlled delay line [10]. This type of delay line reduces layout area by using a delay line that is only a ...
• DLLs lock delay of a voltage-controlled delay line (VCDL) ... duty cycle distortion, resulting in bad spur performance. • A dynamic gate is ...
The VCDL with DCC can reduce the duty cycle distortion of the demodulation signal and thus improve the measurement accuracy of the ToF sensor. This paper is ...
The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency ...