The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware ...

Oct 22, 2024 · In this paper, we present a strategy for run-time profiling to optimize the configuration of a superscalar microprocessor dynamically so as to ...

Abstract: Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while ...

This first generation of "Niagara" SPARC proces- sors implements a power-efficient Chip Multi-Threading (CMT) architecture which maximizes overall ...

The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b ...

The Niagara approach to increasing throughput on commercial server applications involves a dramatic increase in the number of threads supported on the processor ...

Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of ...

The hard- ware hides memory and pipeline stalls on a given thread by scheduling the other threads in the group onto the SPARC pipe with a zero cycle switch ...

•Designed for high bandwidth and low power. •4 way banked 3MB L2 cache. •12 way set associative to handle 32 threads. •Data is 64B interleaved across banks.

The chip-multi- threaded (CMT) architecture achieves high throughput while optimizing performance/watt. Concurrent execution of 32 threads is implemented ...