In this paper, we propose a high level synthesis framework to take into account of the performance/power variation for function units. An effective metric ...

In this paper, we propose a high level synthesis framework to take into account of the performance/power variation for function units. An effective metric ...

In this paper, we apply statistical timing/power analysis to high level synthesis, and develop yield driven synthesis framework so that the impact of process ...

This paper proposes a high level synthesis framework to take into account of the performance/power variation for function units, and shows that the ...

... A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization | As the CMOS technology scales down to

In this paper, we propose a new variation-aware high-level synthesis bind- ing/module selection algorithm, named FastYield, which takes into consideration ...

Dec 6, 2009 · "A Variation Aware High Level Synthesis Framework."; in Proceedings of Design Automation and Test in Europe (DATE), Mar. 2008. Feng Wang ...

Without considering (i) and (ii) in the framework of variation-aware HLS, the synthesis results would be far less accurate in timing, failing in timing closure.

In this paper, we survey and discuss the state-of-art timing variation-aware HLS techniques, with the classification of (1) SSTAs for HLS, (2) HLS framework ...

This paper proposes a high level synthesis framework to take into account of the performance/power variation for function units, and shows that the variation- ...