Abstract: In this work, domino logic with a variable threshold voltage keeper which uses an efficient body bias is proposed. The generator which consists of ...
The variable threshold voltage keeper circuit technique enhances cir- cuit evaluation speed by up to 60% while reducing power dissipa- tion by 35% as compared ...
A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold ...
Jun 30, 2003 · energy efficient operation in domino logic circuits. To reduce contention current, a multi-phase keeper tech- nique has been proposed ...
The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power consumption while maintaining ...
In this work, domino logic with a variable threshold voltage keeper which uses an efficient ... Domino logic with an efficient variable threshold voltage keeper.
A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits.
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Abstract—In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength.
A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits.
In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength of the keeper is achieved ...