Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. Abstract: With aggressive scaling of CMOS technology, different performance ...

aroy5@uic.edu, masud@ece.uic.edu. Abstract- With aggressive scaling of CMOS technology, different performance parameters: latency, bandwidth, repeater.

Bibliographic details on Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.

As technology advances, global interconnects in upper metal layers exhibit significant inductive effect with faster signal rise and fall times.

The impacts of inductance on performance parameters, which were previously based on RC models, are examined and the limitations of these figures of merit ...

One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent.

ABSTRACT. In this paper the impact of width variation is being addressed on transition time, power dissipation and crosstalk noise in coupled inductive ...

The closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective ...

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology ...

Abstract—This paper provides a high level survey of the in- creasing effects of on-chip inductance. These effects are classified.