This paper presents a new test methodology which utilizes the programming language interface (PLI) for performing fault simulation of combinational or full ...

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT 2005: 389-397.

IBM's experience with core-based designs provides insight into methodology, SOC design styles, core design trade-offs, and ASIC design processes.

May 3, 2012 · Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. Pedram A. Riahi Zainalabedin Navabi Fabrizio Lombardi Electrical ...

This paper presents a new test methodology which utilizes the programming language interface (PLI) for performing fault simulation of combinational or full scan ...

Testing of CoreWare based ASICs is emerging as the most challenging problem of the 1990s, and the challenge is how to test the embedded cores and how to ...

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment pp. 389-397. On Generating Pseudo-Functional Delay Fault Tests for Scan Designs pp.

Apr 25, 2024 · Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. ... IP Core Module-Based Mixed Level Serial Fault Simulation ...

Simulating faults of combinational IP core-based SOCs in a PLI environment. Conference Paper. Nov 2005. P.A. Riahi · Zainalabedin ...

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment ... IP Core Module-Based Mixed Level Serial Fault Simulation ...