When a SOI NMOS transistor is exposed to the total ionizing dose (TID) radiation, the edge effect will take place by the onset of parasitic sidewall transistor.
Experimental results show that the edge effect is very sensitive to their layouts. Among the transistors hardened by design, the H-gate and ringed-source ...
Jan 11, 2024 · Experimental results show that the edge effect is very sensitive to their layouts. Among the transistors hardened by design, the H-gate and ...
Semantic Scholar extracted view of "Total-dose-induced edge effect in SOI NMOS transistors with different layouts" by Jie Liu et al.
Sep 23, 2015 · The radiation performance is characterized by transistor threshold voltage shift and transistor leakage currents as a function of the total dose ...
Aug 8, 2008 · the difference in response between the transistors may be caused by the differences in their layout structures, which affect the magnitude ...
The results showed that single-event upset (SEU) can be triggered only when secondary ions hit both the delay transistor and OFF-state NMOS transistor [26].
The radiation performance is characterized by transistor threshold voltage shift and transistor leakage currents as a function of the total dose up to 2.0×106 ...
Missing: edge | Show results with:edge
The purpose of this paper is to evaluate the total dose hardness of fully-depleted SOI MOSFETs on. SIMOX with different gate lengths and different gate.
Missing: NMOS | Show results with:NMOS
Compared with the low-voltage integrated circuits, the high-voltage MOSFET is more sensitive to the total ionizing dose (TID) due to the thicker gate oxide.