%0 Journal Article
%T Formalizing UML State Machines for Automated Verification – A Survey
%+ Modeling and Verification of Distributed Algorithms and Systems (VERIDIS)
%+ Proof-oriented development of computer-based systems (MOSEL)
%+ Tianjin University (TJU)
%+ Nanyang Technological University [Singapour] (NTU)
%+ Laboratoire d'Informatique de Paris-Nord (LIPN)
%+ School of Information Systems  (Singapore Management University - SMU) (SIS - SMU)
%+ National University of Singapore (NUS)
%A André, Étienne
%A Liu, Shuang
%A Liu, Yang
%A Choppy, Christine
%A Sun, Jun
%A Dong, Jin Song
%Z This work is supported by project 9.10.11 "Software Verification from Design to Implementation" of French-Singaporean Programme Merlion.
%Z This is the author version of the manuscript of the same name published in ACM Computing Surveys
%< avec comité de lecture
%@ 0360-0300
%J ACM Computing Surveys
%I Association for Computing Machinery
%V 55
%N 13s
%P 1-47
%8 2023-07-13
%D 2023
%Z 2407.17215
%R 10.1145/3579821
%K UML
%K Semantics
%K Formal specification
%K Formal verification
%Z Computer Science [cs]/Software Engineering [cs.SE]Journal articles
%X The Unified Modeling Language (UML) is a standard for modeling dynamic systems. UML behavioral state machines are used for modeling the dynamic behavior of object-oriented designs. The UML specification, maintained by the Object Management Group (OMG), is documented in natural language (in contrast to formal language). The inherent ambiguity of natural languages may introduce inconsistencies in the resulting state machine model. Formalizing UML state machine specification aims at solving the ambiguity problem and at providing a uniform view to software designers and developers. Such a formalization also aims at providing a foundation for automatic verification of UML state machine models, which can help to find software design vulnerabilities at an early stage and reduce the development cost. We provide here a comprehensive survey of existing work from 1997 to 2021 related to formalizing UML state machine semantics for the purpose of conducting model checking at the design stage.
%G English
%L hal-04661686
%U https://hal.science/hal-04661686
%~ UNIV-PARIS13
%~ CNRS
%~ INRIA
%~ INRIA_TEST
%~ INRIA-LORRAINE
%~ LORIA2
%~ INRIA-NANCY-GRAND-EST
%~ TESTALAIN1
%~ LIPN
%~ UNIV-LORRAINE
%~ INRIA2
%~ LORIA
%~ LORIA-FM
%~ SORBONNE-PARIS-NORD
%~ CONFRENCE-NATIONALE-SUR-LES-APPLICATIONS-PRATIQUES-DE-LINTELLIGENCE-ARTIFICIELLE
%~ ACT-R
%~ INRIA-SINGAPOUR
%~ INRIA-ALLEMAGNE