Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing var... more Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations of the FPGA, but changing configurations incurs reprogramming costs. The fundamental question for FPGA testing is how to determine the minimum number of test configurations and corresponding test vector sequences that will cover all the faults for a given FPGA's fault model. In this paper first two types of fault that can occur in the LUT of a FPGA i.e. data faults and addressing faults have been described. Based on this new fault model it has been shown that only 4 configurations are needed for testing of LUTs in a FPGA. A hierarchical approach is then proposed to solve the problem of controllability and observability while testing entire FPGA. This hierarchical approach is faster compared to the other approaches in literature for FPGA testing. The proposed hierarchical approach is also independent of the fault model and configuration used.
In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which wo... more In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which would not only detect whether the chip is faulty or not but, also provide the information regarding the position and the type of fault present. A modified fault dictionary is prepared that is used to minimize the effort in fault location. The proposed algorithm has two parts: first, generation of optimized fault dictionary, and then usage of this fault dictionary. This modified dictionary also gives a heuristic approach to minimize the number of test vectors required for testing the chip with some trade-off with fault coverage. This proposed algorithm is faster in locating a fault in a chip compared to other classical fault location technique. For validation, POTG Algorithm has been applied to ISCAS’85 Benchmark circuit and results have been obtained.
In the recent years, reversible logic has emerged as a promising technology having its applicatio... more In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. A reversible circuit maps each output vector into a unique input vector, and vice versa. There always has been a hurdle in realization and optimization of reversible circuit. One way of realizing reversible logic is quantum computers. Quantum computing has been a field of growing interest in the last decade because of its promises to reduce power consumption. This paper presents realization of reversible circuits such as adder and multiplier using three different methods which are as follows CMOS logic, Quantum cellular automata (QCA), and jQuantum. Although CMOS don’t take full benefit of reversibility criteria but it is used for functional verification of reversible circuit design. In this paper we have implemented few reversible circuits in CMOS and their layout is presented. QCA is a new technology for realization of quantum circuits. Minimum area full adder has been implemented in QCAD and presented in this paper. This paper also proposes a design of a reversible multiplier with minimum complexity in terms of gates. This multiplier design has been verified using jQuantum which is a JAVA simulator which designs reversible circuits based on quantum wires. A novel design of a 4x4 multiplier has also been proposed. Thus, this paper proposes different methods for realising reversible logic and their optimization techniques.
Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing var... more Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations of the FPGA, but changing configurations incurs reprogramming costs. The fundamental question for FPGA testing is how to determine the minimum number of test configurations and corresponding test vector sequences that will cover all the faults for a given FPGA's fault model. In this paper first two types of fault that can occur in the LUT of a FPGA i.e. data faults and addressing faults have been described. Based on this new fault model it has been shown that only 4 configurations are needed for testing of LUTs in a FPGA. A hierarchical approach is then proposed to solve the problem of controllability and observability while testing entire FPGA. This hierarchical approach is faster compared to the other approaches in literature for FPGA testing. The proposed hierarchical approach is also independent of the fault model and configuration used.
In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which wo... more In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which would not only detect whether the chip is faulty or not but, also provide the information regarding the position and the type of fault present. A modified fault dictionary is prepared that is used to minimize the effort in fault location. The proposed algorithm has two parts: first, generation of optimized fault dictionary, and then usage of this fault dictionary. This modified dictionary also gives a heuristic approach to minimize the number of test vectors required for testing the chip with some trade-off with fault coverage. This proposed algorithm is faster in locating a fault in a chip compared to other classical fault location technique. For validation, POTG Algorithm has been applied to ISCAS’85 Benchmark circuit and results have been obtained.
In the recent years, reversible logic has emerged as a promising technology having its applicatio... more In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. A reversible circuit maps each output vector into a unique input vector, and vice versa. There always has been a hurdle in realization and optimization of reversible circuit. One way of realizing reversible logic is quantum computers. Quantum computing has been a field of growing interest in the last decade because of its promises to reduce power consumption. This paper presents realization of reversible circuits such as adder and multiplier using three different methods which are as follows CMOS logic, Quantum cellular automata (QCA), and jQuantum. Although CMOS don’t take full benefit of reversibility criteria but it is used for functional verification of reversible circuit design. In this paper we have implemented few reversible circuits in CMOS and their layout is presented. QCA is a new technology for realization of quantum circuits. Minimum area full adder has been implemented in QCAD and presented in this paper. This paper also proposes a design of a reversible multiplier with minimum complexity in terms of gates. This multiplier design has been verified using jQuantum which is a JAVA simulator which designs reversible circuits based on quantum wires. A novel design of a 4x4 multiplier has also been proposed. Thus, this paper proposes different methods for realising reversible logic and their optimization techniques.
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Papers by Sumit Raj