Multipliers have become one of the most common components in modern digital Integrated Circuit de... more Multipliers have become one of the most common components in modern digital Integrated Circuit designs. Vedic Mathematics is the earliest method of Indian mathematics which has a unique technique of calculations based on 16 Formulae. The proposed multiplier technique is from” urdhva tiryakbhayam sutra “which is one of the sutras in Vedic mathematics. Architectures of the proposed Vedic multipliers are implemented on ASIC by using CBIC and state-of-the-art implementation technologies. High-level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. All proposed multipliers are synthesized with Synopsys Design Compiler through saed32lvt_ss0p95vn40c library file. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Traditional Wallace Multiplier, Reduced Complexity Wallace multiplier and Dadda multiplier. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power ...
Arbitrary function generators often known as Arbitrary Waveform Generators (AWGs) are becoming in... more Arbitrary function generators often known as Arbitrary Waveform Generators (AWGs) are becoming increasingly important for many military and commercial applications. Many approaches for design and fabrication of AWGs are used. However, all of them suffer from various drawbacks and are therefore not acceptable for all application. A novel approach has therefore been attempted for generating arbitrary waveforms using orthogonal functions. The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used by engineers for various Digital Signal Processing (DSP) applications since such applications require fast processing time in order to meet the challenges of the real time systems. A set of Rademacher and Walsh Functions has been used to develop a standalone arbitrary function generator. The design is targeted to the stateof-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools...
A novel method for designing and realising compact digital circuits by engineering MOSFET gate el... more A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.
A high-performance enhancement-mode charge plasma based gallium nitride (CP-GaN) MOSFET is stimul... more A high-performance enhancement-mode charge plasma based gallium nitride (CP-GaN) MOSFET is stimulated. Here, metals of same work functions are used to induce n - type charge plasma in an undoped GaN film to realise source and drain regions of a GaN MOSFET. The proposed device is not heterostructure like the conventional GaN/AlGaN devices and is hence free from hetero-epitaxial defects and inverse piezoelectric effects, and can have reduced leakage and can be more reliable. An extensive simulation study has revealed that the proposed CP-GaN device exhibits a threshold voltage of 1.4 V, large I ON / I OFF ratio of 10 8 and transconductance ( g m ) of 308 mS/mm.
Abstract In this paper, we propose new structures of lateral bipolar junction transistor (LBJT) o... more Abstract In this paper, we propose new structures of lateral bipolar junction transistor (LBJT) on silicon on insulator (SOI) with improved performance. The proposed devices are lateral bipolar transistors with multi doping zone collector drift region and a thick buried oxide under the collector region. Calibrated simulation studies have revealed that the proposed devices have higher breakdown voltage than the conventional device, that too at higher drift doping concentration. This has resulted in improved tradeoff between the on-resistance and the breakdown voltage of the proposed devices. It has been observed that the proposed device with two collector drift doping zones and a buried oxide thick step results in ∼190% increase in the breakdown voltage than the conventional device. The further increase in the number of collector drift doping zones from two to three has increased the breakdown voltage by 260% than the conventional one. On comparing the proposed devices with the buried oxide double step devices, it has been found that an increase of ∼15–19% in the breakdown voltage is observed in the proposed devices even at higher drift doping concentrations. The use of higher drift doping concentration reduces the on-resistance of the proposed device and thus improves the tradeoff between the breakdown voltage and the on-resistance of the proposed device in comparison to buried oxide double step devices. Further, the use of step doping in the collector drift region has resulted in the reduction of kink effect in the proposed device. Using the mixed mode simulations, the proposed devices have been tested at the circuit level, by designing and simulating inverting amplifiers employing the proposed devices. Both DC and AC analyses of the inverting amplifiers have shown that the proposed devices work well at the circuit level. It has been observed that there is a slight increase in ON delay in the proposed device; however, the OFF delay is more or less same as that of the conventional device.
31st European Photovoltaic Solar Energy Conference and Exhibition
Oxygenated cadmium sulfide (CdS:O) thin films have been prepared by reactive RF magnetron sputter... more Oxygenated cadmium sulfide (CdS:O) thin films have been prepared by reactive RF magnetron sputtering with varying the O partial pressure from 0.08 mTorr to 0.18 mTorr. The quantitative results from the X-ray photoelectron spectroscopy (XPS) show that the relative concentration of oxygen atoms increases considerably with O partial pressure and O atoms are mostly combined with the S atoms to form SO4 complexes. The bandgap of the films were found in the range of 2.65 eV-2.74 eV.The film’s crytallinity was observed to reduce with the increase of O partial pressure. The complete cell was fabricated by sputtering technique with a novel configuration of ‘glass/FTO/ZnO:Sn/CdS:O/CdTe/Cu:C/Ag’. The performances of the ultra-thin cells (CdTe ~ 1μm) were evaluated under illumination of 1.5 AM, and the efficiency of 10.27% was achieved so far.
31st European Photovoltaic Solar Energy Conference and Exhibition
Cadmium Telluride (CdTe) is one of the promising photovoltaic materials for solar cell. The post ... more Cadmium Telluride (CdTe) is one of the promising photovoltaic materials for solar cell. The post deposition treatment is important to improve the structural, electrical and optical properties of the CdTe thin films. Hence comparative study between the thermal annealing and laser annealing was carried out is this study. The analysis portrayed important features of both the thermal annealing and laser annealing processes and both of them improved the film quality. The films were deposited by radio frequency magnetron sputtering in high vacuum condition for 90 minutes at a growth temperature of 300°C. The CdTe thin films were then subjected to post deposition thermal and laser annealing independently. Thermal annealing was done for 15 minutes at a temperature of 400°C in vacuum condition. Laser annealing was done by illuminating the films with laser beam of 532nm wavelength with laser output energy of 60J/pulse, frequency of 10Hz and stage velocity of 0.5mm/sec. The structural analysis...
In this study, the effects of sulfurization temperature on the properties of thermally evaporated... more In this study, the effects of sulfurization temperature on the properties of thermally evaporated Cu2ZnSnS4 (CZTS) thin films were investigated. Molybdenum (Mo) coated soda lime glass (SLG) was used as substrates and stoichiometric CZTS powder (99.95%) was used as the source material. XRD patterns showed that CZTS were formed with preferential orientations of (112) > (220) > (312) for all the investigated films. The intensity of (112) peak is found increasing until a certain temperature indicating that the highest degree of crystallinity is achieved together with secondary phases such as ZnS and SnS. It was confirmed by raman shift at 338 cm−1 from Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM) results showed a trend for surface roughness as well as morphology. From Hall effect measurement, all deposited films exhibited p-type conductivity. From UV–vis spectroscopy measurement, the optical band gap of all the films are found in the range of potential absorbers for CZTS based thin film solar cells.
Page 1. 322 IEEE TRANSACTIONS ON INSTRUMENIAIIOP. AND hlb.ASUKEhltN I . \'01 37. NO ... more Page 1. 322 IEEE TRANSACTIONS ON INSTRUMENIAIIOP. AND hlb.ASUKEhltN I . \'01 37. NO 3. ILINI-10x8 multifunctional OTA-C filter for instrumentation applications, ' ' lEEE Trcm. /~i.siruni. Meus.. vol. IM-36, pp. 13-17. 1987. 1121 T. Altaf. ...
In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MO... more In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MOSCAP) extensions incorporating field-induced quantum confinement (FIQC). Unlike Gate-over-Source (GoSo) TFET having an all-lateral design, dual-MOS (D-MOS) TFET has raised channel/drain regions exhibiting better electrostatics at the 2-D source boundary. At similar dimensions, 2-D-calibrated simulations reveal that under No-FIQC condition, D-MOS exhibits <inline-formula> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> better <inline-formula> <tex-math notation="LaTeX">${I} _{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> along with much improved parasitic leakage in the OFF-state (<inline-formula> <tex-math notation="LaTeX">${V} _{ \mathrm{GS}}=\textsf {0}$ </tex-math></inline-formula> V, <inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {DS}}=\textsf {1}$ </tex-math></inline-formula> V). Energy quantization due to FIQC in the conduction band (CB) near the gate dielectric is captured along with the reshaped carrier density distribution. The delay in the onset of vertical band-to-band tunneling (BTBT), <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{\textsf {BTBT}}$ </tex-math></inline-formula> shift, and deterioration in <inline-formula> <tex-math notation="LaTeX">${I} _{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> are also calculated. We later observe that the use of a dual-metal-gate (DMG) and an unequal lateral/vertical oxide thickness as structural improvements further eliminates the parasitic leakage. In addition, with the gate–drain underlap (<inline-formula> <tex-math notation="LaTeX">${L} _{\textsf {GD}}$ </tex-math></inline-formula>) up to 10 nm, a reduction in intrinsic delay is also observed.
In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET... more In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET. The novelty of the device is that it uses the charge plasma concept to induce n type charge plasma in an undoped GaN film, by employing metal electrodes, to realize source and drain regions of a GaN MOSFET. The proposed device is not a hetero-structure device, like the conventional GaN/AlGaN MOSFET and is hence more reliable and free from the hetero-epitaxial defects, inverse piezoelectric effects, and can have reduced leakage. Further, the proposed device can be fabricated at a reduced thermal budget as it does not possess any doped region. A two dimensional calibrated simulation study of the proposed device has revealed that it exhibits a threshold voltage of 1.4 V, large $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio of $$10 ^{12}$$1012, cutoff frequency ($$f_\mathrm{T}$$fT) of 0.58 GHz, maximum oscillation frequency ($$f_{\mathrm{max}}$$fmax) of 3.2 GHz, transconductance ($$g_{\mathrm{m}}$$gm) of 40 mS/mm and a breakdown voltage of 22 V (at $$L_\mathrm{GD}= 0$$LGD=0). Further, the enhancement mode operation in the proposed device has been realized in a much easier way than that in the state of the art doping less AlGaN/GaN based devices. A process flow for the fabrication of the proposed device is also given.
International Journal of Electrical and Computer Engineering (IJECE), 2018
This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the... more This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here ...
Abstract In this work, we propose and simulate a novel single transistor based transmission gate.... more Abstract In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel combination of NMOS and PMOS transistors in a conventional transmission gate. The proposed device is compact, has reduced number of regions, junctions and interconnects in comparison to the conventional transmission gate. A two dimensional (2D) calibrated simulation study has shown a reduction of 10.42% in average delay and 18.7% in the total power dissipation in the proposed transmission gate in comparison to the conventional Schottky barrier MOSFETs based transmission gate. Furthermore, it has been observed that such a transmission gate action cannot be realised by folding the conventional NMOS and PMOS transistors.
ABSTRACT In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-B... more ABSTRACT In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-BJT) on partial buried oxide (PBOX). The novelty of the proposed LAT-BJT device is the use of PBOX, covering just base and emitter regions only. A two-dimensional (2D) calibrated simulation study of the proposed LAT-BJT device has shown that the proposed LAT-BJT on PBOX’s performance is unique when the PBOX is just covering base and emitter regions. At this length of PBOX, a sharp enhancement in cut-off frequency (fT) (~10 times higher) is achieved in the proposed LAT-BJT on PBOX in comparison to an LAT-BJT on silicon-on-insulator (SOI). The breakdown voltage of the proposed LAT-BJT on PBOX is double than that of the LAT-BJT on SOI device at this PBOX length. A notable enhancement in current gain (β) is observed in the proposed LAT-BJT on PBOX in comparison to the LAT-BJT on bulk device. To check the performance of the proposed LAT-BJT on PBOX at the circuit level, two inverters have been designed and simulated using the mixed-mode simulations of Atlas simulator. It has been observed that the proposed LAT-BJT on PBOX significantly outperforms the conventional LAT-BJT device in switching performance. A notable improvement of 32% in ON delay and 72.9% in OFF delay is obtained in the proposed LAT-BJT on PBOX device in comparison to the conventional LAT-BJT device.
Multipliers have become one of the most common components in modern digital Integrated Circuit de... more Multipliers have become one of the most common components in modern digital Integrated Circuit designs. Vedic Mathematics is the earliest method of Indian mathematics which has a unique technique of calculations based on 16 Formulae. The proposed multiplier technique is from” urdhva tiryakbhayam sutra “which is one of the sutras in Vedic mathematics. Architectures of the proposed Vedic multipliers are implemented on ASIC by using CBIC and state-of-the-art implementation technologies. High-level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. All proposed multipliers are synthesized with Synopsys Design Compiler through saed32lvt_ss0p95vn40c library file. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Traditional Wallace Multiplier, Reduced Complexity Wallace multiplier and Dadda multiplier. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power ...
Arbitrary function generators often known as Arbitrary Waveform Generators (AWGs) are becoming in... more Arbitrary function generators often known as Arbitrary Waveform Generators (AWGs) are becoming increasingly important for many military and commercial applications. Many approaches for design and fabrication of AWGs are used. However, all of them suffer from various drawbacks and are therefore not acceptable for all application. A novel approach has therefore been attempted for generating arbitrary waveforms using orthogonal functions. The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used by engineers for various Digital Signal Processing (DSP) applications since such applications require fast processing time in order to meet the challenges of the real time systems. A set of Rademacher and Walsh Functions has been used to develop a standalone arbitrary function generator. The design is targeted to the stateof-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools...
A novel method for designing and realising compact digital circuits by engineering MOSFET gate el... more A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.
A high-performance enhancement-mode charge plasma based gallium nitride (CP-GaN) MOSFET is stimul... more A high-performance enhancement-mode charge plasma based gallium nitride (CP-GaN) MOSFET is stimulated. Here, metals of same work functions are used to induce n - type charge plasma in an undoped GaN film to realise source and drain regions of a GaN MOSFET. The proposed device is not heterostructure like the conventional GaN/AlGaN devices and is hence free from hetero-epitaxial defects and inverse piezoelectric effects, and can have reduced leakage and can be more reliable. An extensive simulation study has revealed that the proposed CP-GaN device exhibits a threshold voltage of 1.4 V, large I ON / I OFF ratio of 10 8 and transconductance ( g m ) of 308 mS/mm.
Abstract In this paper, we propose new structures of lateral bipolar junction transistor (LBJT) o... more Abstract In this paper, we propose new structures of lateral bipolar junction transistor (LBJT) on silicon on insulator (SOI) with improved performance. The proposed devices are lateral bipolar transistors with multi doping zone collector drift region and a thick buried oxide under the collector region. Calibrated simulation studies have revealed that the proposed devices have higher breakdown voltage than the conventional device, that too at higher drift doping concentration. This has resulted in improved tradeoff between the on-resistance and the breakdown voltage of the proposed devices. It has been observed that the proposed device with two collector drift doping zones and a buried oxide thick step results in ∼190% increase in the breakdown voltage than the conventional device. The further increase in the number of collector drift doping zones from two to three has increased the breakdown voltage by 260% than the conventional one. On comparing the proposed devices with the buried oxide double step devices, it has been found that an increase of ∼15–19% in the breakdown voltage is observed in the proposed devices even at higher drift doping concentrations. The use of higher drift doping concentration reduces the on-resistance of the proposed device and thus improves the tradeoff between the breakdown voltage and the on-resistance of the proposed device in comparison to buried oxide double step devices. Further, the use of step doping in the collector drift region has resulted in the reduction of kink effect in the proposed device. Using the mixed mode simulations, the proposed devices have been tested at the circuit level, by designing and simulating inverting amplifiers employing the proposed devices. Both DC and AC analyses of the inverting amplifiers have shown that the proposed devices work well at the circuit level. It has been observed that there is a slight increase in ON delay in the proposed device; however, the OFF delay is more or less same as that of the conventional device.
31st European Photovoltaic Solar Energy Conference and Exhibition
Oxygenated cadmium sulfide (CdS:O) thin films have been prepared by reactive RF magnetron sputter... more Oxygenated cadmium sulfide (CdS:O) thin films have been prepared by reactive RF magnetron sputtering with varying the O partial pressure from 0.08 mTorr to 0.18 mTorr. The quantitative results from the X-ray photoelectron spectroscopy (XPS) show that the relative concentration of oxygen atoms increases considerably with O partial pressure and O atoms are mostly combined with the S atoms to form SO4 complexes. The bandgap of the films were found in the range of 2.65 eV-2.74 eV.The film’s crytallinity was observed to reduce with the increase of O partial pressure. The complete cell was fabricated by sputtering technique with a novel configuration of ‘glass/FTO/ZnO:Sn/CdS:O/CdTe/Cu:C/Ag’. The performances of the ultra-thin cells (CdTe ~ 1μm) were evaluated under illumination of 1.5 AM, and the efficiency of 10.27% was achieved so far.
31st European Photovoltaic Solar Energy Conference and Exhibition
Cadmium Telluride (CdTe) is one of the promising photovoltaic materials for solar cell. The post ... more Cadmium Telluride (CdTe) is one of the promising photovoltaic materials for solar cell. The post deposition treatment is important to improve the structural, electrical and optical properties of the CdTe thin films. Hence comparative study between the thermal annealing and laser annealing was carried out is this study. The analysis portrayed important features of both the thermal annealing and laser annealing processes and both of them improved the film quality. The films were deposited by radio frequency magnetron sputtering in high vacuum condition for 90 minutes at a growth temperature of 300°C. The CdTe thin films were then subjected to post deposition thermal and laser annealing independently. Thermal annealing was done for 15 minutes at a temperature of 400°C in vacuum condition. Laser annealing was done by illuminating the films with laser beam of 532nm wavelength with laser output energy of 60J/pulse, frequency of 10Hz and stage velocity of 0.5mm/sec. The structural analysis...
In this study, the effects of sulfurization temperature on the properties of thermally evaporated... more In this study, the effects of sulfurization temperature on the properties of thermally evaporated Cu2ZnSnS4 (CZTS) thin films were investigated. Molybdenum (Mo) coated soda lime glass (SLG) was used as substrates and stoichiometric CZTS powder (99.95%) was used as the source material. XRD patterns showed that CZTS were formed with preferential orientations of (112) > (220) > (312) for all the investigated films. The intensity of (112) peak is found increasing until a certain temperature indicating that the highest degree of crystallinity is achieved together with secondary phases such as ZnS and SnS. It was confirmed by raman shift at 338 cm−1 from Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM) results showed a trend for surface roughness as well as morphology. From Hall effect measurement, all deposited films exhibited p-type conductivity. From UV–vis spectroscopy measurement, the optical band gap of all the films are found in the range of potential absorbers for CZTS based thin film solar cells.
Page 1. 322 IEEE TRANSACTIONS ON INSTRUMENIAIIOP. AND hlb.ASUKEhltN I . \&amp;#x27;01 37. NO ... more Page 1. 322 IEEE TRANSACTIONS ON INSTRUMENIAIIOP. AND hlb.ASUKEhltN I . \&amp;#x27;01 37. NO 3. ILINI-10x8 multifunctional OTA-C filter for instrumentation applications, &amp;#x27; &amp;#x27; lEEE Trcm. /~i.siruni. Meus.. vol. IM-36, pp. 13-17. 1987. 1121 T. Altaf. ...
In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MO... more In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MOSCAP) extensions incorporating field-induced quantum confinement (FIQC). Unlike Gate-over-Source (GoSo) TFET having an all-lateral design, dual-MOS (D-MOS) TFET has raised channel/drain regions exhibiting better electrostatics at the 2-D source boundary. At similar dimensions, 2-D-calibrated simulations reveal that under No-FIQC condition, D-MOS exhibits <inline-formula> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> better <inline-formula> <tex-math notation="LaTeX">${I} _{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> along with much improved parasitic leakage in the OFF-state (<inline-formula> <tex-math notation="LaTeX">${V} _{ \mathrm{GS}}=\textsf {0}$ </tex-math></inline-formula> V, <inline-formula> <tex-math notation="LaTeX">${V} _{\textsf {DS}}=\textsf {1}$ </tex-math></inline-formula> V). Energy quantization due to FIQC in the conduction band (CB) near the gate dielectric is captured along with the reshaped carrier density distribution. The delay in the onset of vertical band-to-band tunneling (BTBT), <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{\textsf {BTBT}}$ </tex-math></inline-formula> shift, and deterioration in <inline-formula> <tex-math notation="LaTeX">${I} _{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> are also calculated. We later observe that the use of a dual-metal-gate (DMG) and an unequal lateral/vertical oxide thickness as structural improvements further eliminates the parasitic leakage. In addition, with the gate–drain underlap (<inline-formula> <tex-math notation="LaTeX">${L} _{\textsf {GD}}$ </tex-math></inline-formula>) up to 10 nm, a reduction in intrinsic delay is also observed.
In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET... more In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET. The novelty of the device is that it uses the charge plasma concept to induce n type charge plasma in an undoped GaN film, by employing metal electrodes, to realize source and drain regions of a GaN MOSFET. The proposed device is not a hetero-structure device, like the conventional GaN/AlGaN MOSFET and is hence more reliable and free from the hetero-epitaxial defects, inverse piezoelectric effects, and can have reduced leakage. Further, the proposed device can be fabricated at a reduced thermal budget as it does not possess any doped region. A two dimensional calibrated simulation study of the proposed device has revealed that it exhibits a threshold voltage of 1.4 V, large $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio of $$10 ^{12}$$1012, cutoff frequency ($$f_\mathrm{T}$$fT) of 0.58 GHz, maximum oscillation frequency ($$f_{\mathrm{max}}$$fmax) of 3.2 GHz, transconductance ($$g_{\mathrm{m}}$$gm) of 40 mS/mm and a breakdown voltage of 22 V (at $$L_\mathrm{GD}= 0$$LGD=0). Further, the enhancement mode operation in the proposed device has been realized in a much easier way than that in the state of the art doping less AlGaN/GaN based devices. A process flow for the fabrication of the proposed device is also given.
International Journal of Electrical and Computer Engineering (IJECE), 2018
This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the... more This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here ...
Abstract In this work, we propose and simulate a novel single transistor based transmission gate.... more Abstract In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel combination of NMOS and PMOS transistors in a conventional transmission gate. The proposed device is compact, has reduced number of regions, junctions and interconnects in comparison to the conventional transmission gate. A two dimensional (2D) calibrated simulation study has shown a reduction of 10.42% in average delay and 18.7% in the total power dissipation in the proposed transmission gate in comparison to the conventional Schottky barrier MOSFETs based transmission gate. Furthermore, it has been observed that such a transmission gate action cannot be realised by folding the conventional NMOS and PMOS transistors.
ABSTRACT In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-B... more ABSTRACT In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-BJT) on partial buried oxide (PBOX). The novelty of the proposed LAT-BJT device is the use of PBOX, covering just base and emitter regions only. A two-dimensional (2D) calibrated simulation study of the proposed LAT-BJT device has shown that the proposed LAT-BJT on PBOX’s performance is unique when the PBOX is just covering base and emitter regions. At this length of PBOX, a sharp enhancement in cut-off frequency (fT) (~10 times higher) is achieved in the proposed LAT-BJT on PBOX in comparison to an LAT-BJT on silicon-on-insulator (SOI). The breakdown voltage of the proposed LAT-BJT on PBOX is double than that of the LAT-BJT on SOI device at this PBOX length. A notable enhancement in current gain (β) is observed in the proposed LAT-BJT on PBOX in comparison to the LAT-BJT on bulk device. To check the performance of the proposed LAT-BJT on PBOX at the circuit level, two inverters have been designed and simulated using the mixed-mode simulations of Atlas simulator. It has been observed that the proposed LAT-BJT on PBOX significantly outperforms the conventional LAT-BJT device in switching performance. A notable improvement of 32% in ON delay and 72.9% in OFF delay is obtained in the proposed LAT-BJT on PBOX device in comparison to the conventional LAT-BJT device.
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Papers by A.R Alamoud