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In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitat... more In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitative analysis of image content. However, color variation in image samples makes it challenging to produce reliable results. This paper introduces a complete normalization scheme to address the problem of color variation in histopathology images jointly caused by inconsistent biopsy staining and non-standard imaging condition. Method: Different from existing normalization methods that either address partial cause of color variation or lump them together, our method identifies causes of color variation based on a microscopic imaging model and addresses inconsistency in biopsy imaging and staining by an illuminant normalization module and a spectral normalization module, respectively. In evaluation, we use two public datasets that are representative of histo-pathology images commonly received in clinics to examine the proposed method from the aspects of robustness to system settings, perform...
Through this work, a low complexity and an efficient DWT processor based design is proposed for i... more Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. To enhance the speed for this proposed system, a serial architecture with partial pipelined structure is introduced along with good utilization in accomplished with resources availability in target FPGA. The new model is designed by System Generator blocks using the simulink Simulation. A Matlab tool along with Xilinx synthesis tool (XST) also used. The final results give the power consumption of 117mW at 28 degree/c in seam temperature. An improvement of speed in 15% with better Signal to noise ratio is obtained from the comparison result.
In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitat... more In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitative analysis of image content. However, color variation in image samples makes it challenging to produce reliable results. This paper introduces a complete normalization scheme to address the problem of color variation in histo-pathology images jointly caused by inconsistent biopsy staining and non-standard imaging condition. Method: Different from existing normalization methods that either address partial cause of color variation or lump them together, our method identifies causes of color variation based on a microscopic imaging model and addresses inconsistency in biopsy imaging and staining by an illuminant normalization module and a spectral normalization module, respectively. In evaluation, we use two public datasets that are representative of histo-pathology images commonly received in clinics to examine the proposed method from the aspects of robustness to system settings, performance consistency against achromatic pixels, and normalization effectiveness in terms of histological information preservation. Results: As the saturation-weighted statistics proposed in this work generates stable and reliable color cues for stain normalization, our scheme is robust to system parameters and insensitive to image content and achromatic colors. Conclusion: Extensive experimentation suggests that our approach outperforms state-ofthe-art normalization methods as the proposed method is the only approach that succeeds to preserve histological information after normalization. Significance: The proposed color normalization solution would be useful to mitigate effects of color variation in pathology images on subsequent quantitative analysis.
— Through this work, a low complexity and an efficient DWT processor based design is proposed for... more — Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. In the proposed processor design, a pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and also with Matlab tool. The results show that proposed design can consume power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed with better Signal to noise Ratio.
Here an efficient combined single path delay commutator with feedback radix-2 pipelined fast Four... more Here an efficient combined single path delay commutator with feedback radix-2 pipelined fast Fourier trans form , which includes log2 N − 1 SDC stages, and another 1 SDF stage. The SDC processing engine is give to achieve 110% hardware resource utilization by sharing the common arithmetic a resource in the time-multiplexed approach, this including both adders and multipliers. Thus, the required number of the complex multipliers is to reduced to log4 N − 1.5, compared with log2 N − 1 for the other radix-2 SDC/SDF architectures. In addition, the new architecture requires a roughly minimum number of complex adders log2 N + 1 and complex delay memory 2N + 2.5 log2 N − 2.5.
Comparator is one of the fundamental building blocks in most analog to digital converters. Many h... more Comparator is one of the fundamental building blocks in most analog to digital converters. Many high speed analog to digital converters such as flash analog to digital converter require high speed and low power comparators. A new double tail comparator is designed, where the circuit of a conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors the positive feedback during the regeneration is strengthened which results in remarkably reduced delay time. Post layout simulation results in a 0.18µm technology confirm the analysis results. It is shown that in the switching transistors using dynamic comparator, both the power consumption and delay time are significantly reduced. Power consumption of conventional double tail comparator is 12µW in 0.8v and power is reduced to 9.5μW in double tail comparator using switching transistorswith the same supply voltage.
An event-driven simulator for performance evaluation and modeling of parallel processing systems ... more An event-driven simulator for performance evaluation and modeling of parallel processing systems and parallel algorithms is presented. The system topology and architectural details are input to the simulator by means of a menu-driven graphics interface. The application program to be simulated is written in the metalanguage provided and mapped onto the system. The simulator produces performance metrics of resource utilization and process sojourns in various states. A trace file containing the log of the system, execution snapshots, and a module for graphical execution animation is provided for further analyses
— Through this work, a low complexity and an efficient DWT processor based design is proposed for... more — Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. In the proposed processor design, a pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and also with Matlab tool. The results show that proposed design can consume power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed with better Signal to noise Ratio.
In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitat... more In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitative analysis of image content. However, color variation in image samples makes it challenging to produce reliable results. This paper introduces a complete normalization scheme to address the problem of color variation in histopathology images jointly caused by inconsistent biopsy staining and non-standard imaging condition. Method: Different from existing normalization methods that either address partial cause of color variation or lump them together, our method identifies causes of color variation based on a microscopic imaging model and addresses inconsistency in biopsy imaging and staining by an illuminant normalization module and a spectral normalization module, respectively. In evaluation, we use two public datasets that are representative of histo-pathology images commonly received in clinics to examine the proposed method from the aspects of robustness to system settings, perform...
Through this work, a low complexity and an efficient DWT processor based design is proposed for i... more Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. To enhance the speed for this proposed system, a serial architecture with partial pipelined structure is introduced along with good utilization in accomplished with resources availability in target FPGA. The new model is designed by System Generator blocks using the simulink Simulation. A Matlab tool along with Xilinx synthesis tool (XST) also used. The final results give the power consumption of 117mW at 28 degree/c in seam temperature. An improvement of speed in 15% with better Signal to noise ratio is obtained from the comparison result.
In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitat... more In digital histo-pathology, tasks of segmentation and disease diagnosis are achieved by quantitative analysis of image content. However, color variation in image samples makes it challenging to produce reliable results. This paper introduces a complete normalization scheme to address the problem of color variation in histo-pathology images jointly caused by inconsistent biopsy staining and non-standard imaging condition. Method: Different from existing normalization methods that either address partial cause of color variation or lump them together, our method identifies causes of color variation based on a microscopic imaging model and addresses inconsistency in biopsy imaging and staining by an illuminant normalization module and a spectral normalization module, respectively. In evaluation, we use two public datasets that are representative of histo-pathology images commonly received in clinics to examine the proposed method from the aspects of robustness to system settings, performance consistency against achromatic pixels, and normalization effectiveness in terms of histological information preservation. Results: As the saturation-weighted statistics proposed in this work generates stable and reliable color cues for stain normalization, our scheme is robust to system parameters and insensitive to image content and achromatic colors. Conclusion: Extensive experimentation suggests that our approach outperforms state-ofthe-art normalization methods as the proposed method is the only approach that succeeds to preserve histological information after normalization. Significance: The proposed color normalization solution would be useful to mitigate effects of color variation in pathology images on subsequent quantitative analysis.
— Through this work, a low complexity and an efficient DWT processor based design is proposed for... more — Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. In the proposed processor design, a pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and also with Matlab tool. The results show that proposed design can consume power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed with better Signal to noise Ratio.
Here an efficient combined single path delay commutator with feedback radix-2 pipelined fast Four... more Here an efficient combined single path delay commutator with feedback radix-2 pipelined fast Fourier trans form , which includes log2 N − 1 SDC stages, and another 1 SDF stage. The SDC processing engine is give to achieve 110% hardware resource utilization by sharing the common arithmetic a resource in the time-multiplexed approach, this including both adders and multipliers. Thus, the required number of the complex multipliers is to reduced to log4 N − 1.5, compared with log2 N − 1 for the other radix-2 SDC/SDF architectures. In addition, the new architecture requires a roughly minimum number of complex adders log2 N + 1 and complex delay memory 2N + 2.5 log2 N − 2.5.
Comparator is one of the fundamental building blocks in most analog to digital converters. Many h... more Comparator is one of the fundamental building blocks in most analog to digital converters. Many high speed analog to digital converters such as flash analog to digital converter require high speed and low power comparators. A new double tail comparator is designed, where the circuit of a conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors the positive feedback during the regeneration is strengthened which results in remarkably reduced delay time. Post layout simulation results in a 0.18µm technology confirm the analysis results. It is shown that in the switching transistors using dynamic comparator, both the power consumption and delay time are significantly reduced. Power consumption of conventional double tail comparator is 12µW in 0.8v and power is reduced to 9.5μW in double tail comparator using switching transistorswith the same supply voltage.
An event-driven simulator for performance evaluation and modeling of parallel processing systems ... more An event-driven simulator for performance evaluation and modeling of parallel processing systems and parallel algorithms is presented. The system topology and architectural details are input to the simulator by means of a menu-driven graphics interface. The application program to be simulated is written in the metalanguage provided and mapped onto the system. The simulator produces performance metrics of resource utilization and process sojourns in various states. A trace file containing the log of the system, execution snapshots, and a module for graphical execution animation is provided for further analyses
— Through this work, a low complexity and an efficient DWT processor based design is proposed for... more — Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. In the proposed processor design, a pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and also with Matlab tool. The results show that proposed design can consume power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed with better Signal to noise Ratio.
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