Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to p... more Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCo...
Proceedings of the great lakes symposium on VLSI, 2012
Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random t... more Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by
ACM Transactions on Design Automation of Electronic Systems, 2000
This paper presents a novel approach to the problem of optimizing combinational circuits for low ... more This paper presents a novel approach to the problem of optimizing combinational circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than it would at the technology-independent level. After each node's switching activity in the circuit is determined, high-power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and learning is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power. Bes...
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The effects of temperature on delay depend on several parameters, such as cell size, load, supply... more The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-Vt design; in particular, we show how traditional dual-Vt optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). T... more In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). These diagrams extend BDD'sby allowing values from an arbitrary finite domain to be associatedwith the terminal nodes. We present a treatment foundedin boolean algebras and discuss algorithms and results in applicationslike matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADD's to logicsynthesis, formal verification, and testing of digital systems. 1 IntroductionBinary Decision Diagrams (BDD's) ...
Soft errors are going to play an increasingly critical role in logic design, as power consumption... more Soft errors are going to play an increasingly critical role in logic design, as power consumption drives CMOS scaling to ever lower supply voltages and device sizes. Both of these downscaling approaches contribute to significantly increased logic signal noise variance. This paper introduces a new methodology for predicting noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS inverters operated at low supply voltage. These distributions are essential to computing the probability of soft errors. The radiation-induced SER is not considered here.
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the sta... more Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the stability margin with respect to thermal noise and raising the probability for thermally-induced soft errors. Given the long time scale of noise-induced soft errors, conventional Monte Carlo simulations cannot be used to predict error rates and alternative approaches are needed. In this paper, the analysis of thermal
Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to p... more Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCo...
Proceedings of the great lakes symposium on VLSI, 2012
Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random t... more Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by
ACM Transactions on Design Automation of Electronic Systems, 2000
This paper presents a novel approach to the problem of optimizing combinational circuits for low ... more This paper presents a novel approach to the problem of optimizing combinational circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than it would at the technology-independent level. After each node's switching activity in the circuit is determined, high-power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and learning is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power. Bes...
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The effects of temperature on delay depend on several parameters, such as cell size, load, supply... more The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-Vt design; in particular, we show how traditional dual-Vt optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). T... more In this paper we present theory and experiments on the AlgebraicDecision Diagrams (ADD's). These diagrams extend BDD'sby allowing values from an arbitrary finite domain to be associatedwith the terminal nodes. We present a treatment foundedin boolean algebras and discuss algorithms and results in applicationslike matrix multiplication and shortest path algorithms. Furthermore, we outline possible applications of ADD's to logicsynthesis, formal verification, and testing of digital systems. 1 IntroductionBinary Decision Diagrams (BDD's) ...
Soft errors are going to play an increasingly critical role in logic design, as power consumption... more Soft errors are going to play an increasingly critical role in logic design, as power consumption drives CMOS scaling to ever lower supply voltages and device sizes. Both of these downscaling approaches contribute to significantly increased logic signal noise variance. This paper introduces a new methodology for predicting noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS inverters operated at low supply voltage. These distributions are essential to computing the probability of soft errors. The radiation-induced SER is not considered here.
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the sta... more Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the stability margin with respect to thermal noise and raising the probability for thermally-induced soft errors. Given the long time scale of noise-induced soft errors, conventional Monte Carlo simulations cannot be used to predict error rates and alternative approaches are needed. In this paper, the analysis of thermal
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Papers by R. Bahar