The rapid adoption of Advanced Driver Assistance Systems (ADAS) in modern vehicles, aiming to ele... more The rapid adoption of Advanced Driver Assistance Systems (ADAS) in modern vehicles, aiming to elevate driving safety and experience, necessitates the real-time processing of high-definition video data. This requirement brings about considerable computational complexity and memory demands, highlighting a critical research void for a design integrating high FPS throughput with optimal Mean Average Precision (mAP) and Mean Intersection over Union (mIoU). Performance improvement at lower costs, multi-tasking ability on a single hardware platform, and flawless incorporation into memory-constrained devices are also essential for boosting ADAS performance. Addressing these challenges, this study proposes an ADAS multi-task learning hardware-software co-design approach underpinned by the Kria KV260 Multi-Processor System-on-Chip Field Programmable Gate Array (MPSoC-FPGA) platform. The approach facilitates efficient real-time execution of deep learning algorithms specific to ADAS applications. Utilizing the BDD100K+Waymo, KITTI, and CityScapes datasets, our ADAS multi-task learning system endeavours to provide accurate and efficient multi-object detection, segmentation, and lane and drivable area detection in road images. The system deploys a segmentation-based object detection strategy, using a ResNet-18 backbone encoder and a Single Shot Detector architecture, coupled with quantization-aware training to augment inference performance without compromising accuracy. The ADAS multi-task learning offers customization options for various ADAS applications and can be further optimized for increased precision and reduced memory usage. Experimental results showcase the system's capability to perform real-time multi-class object detection, segmentation, line detection, and drivable area detection on road images at approximately 25.4 FPS using a 1920 × 1080p Full HD camera. Impressively, the quantized model has demonstrated a 51% mAP for object detection, 56.62% mIoU for image segmentation, 43.86% mIoU for line detection, and 81.56% IoU for drivable area identification, reinforcing its high efficacy and precision. The findings underscore that the proposed ADAS multi-task learning system is a practical, reliable, and effective solution for real-world applications.
2020 International Symposium on Fundamentals of Electrical Engineering (ISFEE)
Image processing is the most preferred technique in Computer-Aided Design (CAD) studies, and ther... more Image processing is the most preferred technique in Computer-Aided Design (CAD) studies, and therefore the enhancement of image processing plays an essential role in the advancement of technology. The primary purpose of this study is to examine the effect of fixed threshold value on images of different sizes when using the binarization method in image processing. The analyzes are made based on the change in the detection accuracy percentage of the K-Nearest Neighbor (k-NN), Support Vector Machine (SVM), and Convolutional Neural Networks (CNN) classification methods on the MATLAB software platform. At the same time, the effect of the binarization threshold value on images with different pixel dimensions (8x8, 16x16, 32x32, 64x64, and 128x128) are investigated. CNN classification obtained the best accuracy percentage in the used malaria disease blood cell data 97.5%, followed by k-NN with 95% and SVM with 91.5%.
This article appeared in a journal published by Elsevier. The attached copy is furnished to the a... more This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are
Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current elec... more Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current electronic design applications such as signal or image processing and digital communications because of the remarkable selectivity computational efficiency. Fast and efficient information processing requires a dedicated microprocessor or a digital signal processor that may not always be available or provide enough performance. In such scenarios, designers can configure FPGAs for processing digitized signals. One of the most popular signal processing applications is filtering. Unlike the Infinite Impulse Response (IIR) filters, FIR filters do not have analog equivalent circuits. For this purpose, continuous time-discrete time conversion is not possible with the help of transforms. Because analog filters cannot have a finite impulse response, the design methods of FIR filters can be made as windowing method, pulse response truncation, and optimal filter design method. Considering this information, it aims to digitally separate two signals with different frequencies (2.4 kHz and 4.2 kHz), which are given to the input as analog, to obtain the desired information signal and suppress other signals. We preferred to use LabVIEW graphical programming language to get the digital FIR filter coefficients. We selected rectangular windowing, set the digital filter's sampling frequency as 18720 Hz, and determined the filter's coefficient with high-frequency resolution as 24. Using filter coefficients in the real-time FPGA-VHDL environment, we showed the performance and resource consumption. LabVIEW is used for simulation as well as obtaining filter coefficients. In addition, we compared both simulation and real-time FPGA-VHDL application output waveforms and examined both platforms' advantages and disadvantages.
2019 International Symposium on Advanced Electrical and Communication Technologies (ISAECT), 2019
This paper proposes the usage of Field Programmable Gate Arrays (FPGA) for fault distance detecti... more This paper proposes the usage of Field Programmable Gate Arrays (FPGA) for fault distance detection and positioning of an underground cable by using GSM/GPRS. This task was produced using Very High Speed Integrated Circuit Hardware Description Languages (VHDL) and implemented on Basys-3 FPGA board by using Xilinx Vivado Design Suite 18.1. Deciding the separation of underground power line fault from the base station was done by using FPGA and Global System for Mobile Communication/General Packet Radio Service (GSM/GPRS) module. The main fault types are three phase symmetrical short circuit fault, two phase-to-earth short-circuit fault, phase-to-phase short circuit fault, phase-to-earth short circuit fault and open-circuit fault. In this study, only two types of faults were taken into consideration. The first of them is phaseto-earth short-circuit fault, while the other one is open circuit fault with broken in transmission line and both simulated by using LTspice.
Abstract. This paper presents an alternative approach for dynamic par-tial self-reconfiguration t... more Abstract. This paper presents an alternative approach for dynamic par-tial self-reconfiguration that enables a Field Programmable Gate Array (FPGA) to reconfigure itself dynamically and partially through a parallel configuration access port (PCAP) under the control of the stand alone PCAP core within the FPGA instead of using an embedded processor. The reconfiguration process is accomplished without an internal configu-ration access port(ICAP), which should be used either with MicroBlaze soft core or with PowerPC hard core using HWICAP core for the On-Chip Peripheral Bus (OPB)[6]. However, the stand alone PCAP core needs neither HWICAP core nor the OPB bus interface. The PCAP core needs only 324 slices, which is approximately 16 % of a Spartan-3S200 FPGA. The dynamic partial self-reconfiguration via PCAP core works up to 50Mbyte/s. This approach has been implemented on a pure Spartan-3 FPGA from Xilinx, but it can also be used for any other FPGA architectures, such as Virtex-II(Pro)...
Ozet. E-Belgeler gunumuzde sirketler tarafindan yaygin olarak kullanilmaktadir. Bu makalede islet... more Ozet. E-Belgeler gunumuzde sirketler tarafindan yaygin olarak kullanilmaktadir. Bu makalede isletmelerde olusturulan ham haldeki (or. csv, xml, txt, xls, xlsx formatlari) e-Belgelerin yine isletme tarafinda isletilmesi, yazdirilmasi ve sunucu vasitasiyla karsi tarafa gonderilmesi ele alinmaktadir. E-Belge ornegi olarak, gunumuzde isletmeler tarafindan kullanilmak zorunda olan e-Fatura belgeleri uzerinde calistik. Onerdigimiz cozum, e-Fatura donusum ve yazdirma islemlerinin en kisa zamanda ve ag trafigini asgari seviyeye indirecek sekilde mukellefin yerelinde yapma esasina dayanmaktadir. Gelistirdigimiz yazilim ilk olarak ham haldeki e-Fatura’yi goruntulenebilir (or. html) ve ardindan yazdirilabilir bicime (or. pdf formati) donusturmektedir. Yine bu calisma kapsaminda e-Fatura belgesinin bir yazici araciligiyla ciktisi alinip, gerektiginde isletmenin belirli musterilerine yazdirilabilir ve goruntulenebilir hali e-posta araciligiyla gonderilmektedir. Calisma kapsaminda e-Fatura belges...
This paper presents a powerful processing technique for fast and energyefficient image filtering ... more This paper presents a powerful processing technique for fast and energyefficient image filtering algorithm focusing energy and time-sensitive embedded and robotic platforms. Digital video processing is getting more and more popular in battery-powered devices like mobile robots and smartphones whereas in most cases, it leads overhead on the main central processing unit (CPU) and it consumes a significant amount of energy from the battery. It is suitable for parallelism since there is no data dependency between the steps of the two-dimensional convolution algorithm. We propose a vector version of the two-dimensional convolution algorithm, which can run parallel on embedded processors that has general purpose graphic processing unit (GPGPU), to reduce computation time and energy consumption. Our in-depth experiments shows that using GPGPU could reduce the execution time while guaranteeing lower power consumption and offloading the system CPU. Experimental results showed that we achieved up to 105 times faster operation and 100 times less energy consumption compared to the CPU implementation. Besides, we reduced the CPU overhead up to 10 times.
2019 IEEE 13th International Conference on Application of Information and Communication Technologies (AICT), 2019
This work demonstrates the application and operation principle of a stepper motor to enable the r... more This work demonstrates the application and operation principle of a stepper motor to enable the rotation of solar panels using an FPGA-based Basys3 circuit board coded with the Very High Speed Integrated Circuit Hardware Description Language (VHDL). Step motors are used for the solar panels to follow the sun both vertically (Elevation) and horizontally (Azimuth). The calculation actualized on FPGA permits a considerable abatement of the equal preparing time created by various speed controllers. Speed control of the system was made using VHDL code, Register Transfer Level (RTL) digital hardware structure was created with this code block. To obtain delayed pulse duration applied to the motor, the 50 MHz oscillator frequency provided by the Basys-3 card is divided into lower frequencies ranging from 2 to 10 ms [1] [2]. In this case, the angle of rotation, direction and speed of the motor changes according to the position of the sun. The biggest advantage of using FPGAs instead of a discrete digital component (micro-controllers with active components) in such applications is that they are made very fast and coarse changes during design and that the whole design is achieved as a single buried system. The total programmable hardware structure (utilization of FPGA capacity) used for this project is almost 5% of the total source. All framework takes a shot at an inserted framework without a PC interface.
2018 IEEE 12th International Conference on Application of Information and Communication Technologies (AICT), 2018
Outliers in the data are very common for various fields. So filtering the data is prominent both ... more Outliers in the data are very common for various fields. So filtering the data is prominent both for computing the desired result for a data set correctly or noticing unusual behaviours. In this case study, outlier detection is used to detect false ads, which are placed in the wrong category or have the wrong values, in a real estate sale website. To accomplish this, two websites are crawled, and the real estates with the unexpectedly low or high price per meter-square value are considered as the outlier candidates. To detect outliers, five outlier detection algorithms are run separately and majority voting is used to determine the absolute result, the average price per meter-square in the location. Evaluating the results of algorithms by majority voting, enabled to tolerate deficiencies of an algorithm by others automatically with some other benefits as well.
Bu makalede i3letmede olu3turulan ham haldeki (ör. sv, xml, txt, xls, xlsx formatlar ) elektronik... more Bu makalede i3letmede olu3turulan ham haldeki (ör. sv, xml, txt, xls, xlsx formatlar ) elektronik Fatura verilerinin i3letme taraf nda i3letilmesi, yazd r lmas ve sunu u vas tas yla kar3 tarafa gönderilmesini sa§layan linux tabanl gömülü kart n tasar m ve bu sistemin aksakl §a dayan kl l § ele al nmaktad r. Bu bildiride e-Fatura ve e-Ar3iv fatura dönü3ümlerinden sorumlu olan, aksakl §a dayan kl ve da§ t k bir yap ya sahip olan gömülü DIARIST sistemi anlat lmaktad r. DIARIST sistemi kullan taraf nda bulunan, özelle3mi3 bir gömülü sistem üzerinde çal 3an, çoklu uygulamalara sahip, ar3ivleme amaçl hem uzaktaki sunu u ile etkile3imde olan ve hem de yerelde bulunan kullan (sat ) ve yaz ile haberle3en bir yap d r. DIARIST sistemleri çoklu olup, her biri do§rudan uzakta bulunan sunu u ile etkile3im halindedir. DIARIST sistemi kesintisiz hizmet vermek zorundad r: çünkü bu sistem vergi mükelle eri için mahrem olan, nansal verileri içermekte ve kullan taraf nda çal 3maktad r. Bu çal 3mada DIA...
The rapid adoption of Advanced Driver Assistance Systems (ADAS) in modern vehicles, aiming to ele... more The rapid adoption of Advanced Driver Assistance Systems (ADAS) in modern vehicles, aiming to elevate driving safety and experience, necessitates the real-time processing of high-definition video data. This requirement brings about considerable computational complexity and memory demands, highlighting a critical research void for a design integrating high FPS throughput with optimal Mean Average Precision (mAP) and Mean Intersection over Union (mIoU). Performance improvement at lower costs, multi-tasking ability on a single hardware platform, and flawless incorporation into memory-constrained devices are also essential for boosting ADAS performance. Addressing these challenges, this study proposes an ADAS multi-task learning hardware-software co-design approach underpinned by the Kria KV260 Multi-Processor System-on-Chip Field Programmable Gate Array (MPSoC-FPGA) platform. The approach facilitates efficient real-time execution of deep learning algorithms specific to ADAS applications. Utilizing the BDD100K+Waymo, KITTI, and CityScapes datasets, our ADAS multi-task learning system endeavours to provide accurate and efficient multi-object detection, segmentation, and lane and drivable area detection in road images. The system deploys a segmentation-based object detection strategy, using a ResNet-18 backbone encoder and a Single Shot Detector architecture, coupled with quantization-aware training to augment inference performance without compromising accuracy. The ADAS multi-task learning offers customization options for various ADAS applications and can be further optimized for increased precision and reduced memory usage. Experimental results showcase the system's capability to perform real-time multi-class object detection, segmentation, line detection, and drivable area detection on road images at approximately 25.4 FPS using a 1920 × 1080p Full HD camera. Impressively, the quantized model has demonstrated a 51% mAP for object detection, 56.62% mIoU for image segmentation, 43.86% mIoU for line detection, and 81.56% IoU for drivable area identification, reinforcing its high efficacy and precision. The findings underscore that the proposed ADAS multi-task learning system is a practical, reliable, and effective solution for real-world applications.
2020 International Symposium on Fundamentals of Electrical Engineering (ISFEE)
Image processing is the most preferred technique in Computer-Aided Design (CAD) studies, and ther... more Image processing is the most preferred technique in Computer-Aided Design (CAD) studies, and therefore the enhancement of image processing plays an essential role in the advancement of technology. The primary purpose of this study is to examine the effect of fixed threshold value on images of different sizes when using the binarization method in image processing. The analyzes are made based on the change in the detection accuracy percentage of the K-Nearest Neighbor (k-NN), Support Vector Machine (SVM), and Convolutional Neural Networks (CNN) classification methods on the MATLAB software platform. At the same time, the effect of the binarization threshold value on images with different pixel dimensions (8x8, 16x16, 32x32, 64x64, and 128x128) are investigated. CNN classification obtained the best accuracy percentage in the used malaria disease blood cell data 97.5%, followed by k-NN with 95% and SVM with 91.5%.
This article appeared in a journal published by Elsevier. The attached copy is furnished to the a... more This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are
Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current elec... more Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current electronic design applications such as signal or image processing and digital communications because of the remarkable selectivity computational efficiency. Fast and efficient information processing requires a dedicated microprocessor or a digital signal processor that may not always be available or provide enough performance. In such scenarios, designers can configure FPGAs for processing digitized signals. One of the most popular signal processing applications is filtering. Unlike the Infinite Impulse Response (IIR) filters, FIR filters do not have analog equivalent circuits. For this purpose, continuous time-discrete time conversion is not possible with the help of transforms. Because analog filters cannot have a finite impulse response, the design methods of FIR filters can be made as windowing method, pulse response truncation, and optimal filter design method. Considering this information, it aims to digitally separate two signals with different frequencies (2.4 kHz and 4.2 kHz), which are given to the input as analog, to obtain the desired information signal and suppress other signals. We preferred to use LabVIEW graphical programming language to get the digital FIR filter coefficients. We selected rectangular windowing, set the digital filter's sampling frequency as 18720 Hz, and determined the filter's coefficient with high-frequency resolution as 24. Using filter coefficients in the real-time FPGA-VHDL environment, we showed the performance and resource consumption. LabVIEW is used for simulation as well as obtaining filter coefficients. In addition, we compared both simulation and real-time FPGA-VHDL application output waveforms and examined both platforms' advantages and disadvantages.
2019 International Symposium on Advanced Electrical and Communication Technologies (ISAECT), 2019
This paper proposes the usage of Field Programmable Gate Arrays (FPGA) for fault distance detecti... more This paper proposes the usage of Field Programmable Gate Arrays (FPGA) for fault distance detection and positioning of an underground cable by using GSM/GPRS. This task was produced using Very High Speed Integrated Circuit Hardware Description Languages (VHDL) and implemented on Basys-3 FPGA board by using Xilinx Vivado Design Suite 18.1. Deciding the separation of underground power line fault from the base station was done by using FPGA and Global System for Mobile Communication/General Packet Radio Service (GSM/GPRS) module. The main fault types are three phase symmetrical short circuit fault, two phase-to-earth short-circuit fault, phase-to-phase short circuit fault, phase-to-earth short circuit fault and open-circuit fault. In this study, only two types of faults were taken into consideration. The first of them is phaseto-earth short-circuit fault, while the other one is open circuit fault with broken in transmission line and both simulated by using LTspice.
Abstract. This paper presents an alternative approach for dynamic par-tial self-reconfiguration t... more Abstract. This paper presents an alternative approach for dynamic par-tial self-reconfiguration that enables a Field Programmable Gate Array (FPGA) to reconfigure itself dynamically and partially through a parallel configuration access port (PCAP) under the control of the stand alone PCAP core within the FPGA instead of using an embedded processor. The reconfiguration process is accomplished without an internal configu-ration access port(ICAP), which should be used either with MicroBlaze soft core or with PowerPC hard core using HWICAP core for the On-Chip Peripheral Bus (OPB)[6]. However, the stand alone PCAP core needs neither HWICAP core nor the OPB bus interface. The PCAP core needs only 324 slices, which is approximately 16 % of a Spartan-3S200 FPGA. The dynamic partial self-reconfiguration via PCAP core works up to 50Mbyte/s. This approach has been implemented on a pure Spartan-3 FPGA from Xilinx, but it can also be used for any other FPGA architectures, such as Virtex-II(Pro)...
Ozet. E-Belgeler gunumuzde sirketler tarafindan yaygin olarak kullanilmaktadir. Bu makalede islet... more Ozet. E-Belgeler gunumuzde sirketler tarafindan yaygin olarak kullanilmaktadir. Bu makalede isletmelerde olusturulan ham haldeki (or. csv, xml, txt, xls, xlsx formatlari) e-Belgelerin yine isletme tarafinda isletilmesi, yazdirilmasi ve sunucu vasitasiyla karsi tarafa gonderilmesi ele alinmaktadir. E-Belge ornegi olarak, gunumuzde isletmeler tarafindan kullanilmak zorunda olan e-Fatura belgeleri uzerinde calistik. Onerdigimiz cozum, e-Fatura donusum ve yazdirma islemlerinin en kisa zamanda ve ag trafigini asgari seviyeye indirecek sekilde mukellefin yerelinde yapma esasina dayanmaktadir. Gelistirdigimiz yazilim ilk olarak ham haldeki e-Fatura’yi goruntulenebilir (or. html) ve ardindan yazdirilabilir bicime (or. pdf formati) donusturmektedir. Yine bu calisma kapsaminda e-Fatura belgesinin bir yazici araciligiyla ciktisi alinip, gerektiginde isletmenin belirli musterilerine yazdirilabilir ve goruntulenebilir hali e-posta araciligiyla gonderilmektedir. Calisma kapsaminda e-Fatura belges...
This paper presents a powerful processing technique for fast and energyefficient image filtering ... more This paper presents a powerful processing technique for fast and energyefficient image filtering algorithm focusing energy and time-sensitive embedded and robotic platforms. Digital video processing is getting more and more popular in battery-powered devices like mobile robots and smartphones whereas in most cases, it leads overhead on the main central processing unit (CPU) and it consumes a significant amount of energy from the battery. It is suitable for parallelism since there is no data dependency between the steps of the two-dimensional convolution algorithm. We propose a vector version of the two-dimensional convolution algorithm, which can run parallel on embedded processors that has general purpose graphic processing unit (GPGPU), to reduce computation time and energy consumption. Our in-depth experiments shows that using GPGPU could reduce the execution time while guaranteeing lower power consumption and offloading the system CPU. Experimental results showed that we achieved up to 105 times faster operation and 100 times less energy consumption compared to the CPU implementation. Besides, we reduced the CPU overhead up to 10 times.
2019 IEEE 13th International Conference on Application of Information and Communication Technologies (AICT), 2019
This work demonstrates the application and operation principle of a stepper motor to enable the r... more This work demonstrates the application and operation principle of a stepper motor to enable the rotation of solar panels using an FPGA-based Basys3 circuit board coded with the Very High Speed Integrated Circuit Hardware Description Language (VHDL). Step motors are used for the solar panels to follow the sun both vertically (Elevation) and horizontally (Azimuth). The calculation actualized on FPGA permits a considerable abatement of the equal preparing time created by various speed controllers. Speed control of the system was made using VHDL code, Register Transfer Level (RTL) digital hardware structure was created with this code block. To obtain delayed pulse duration applied to the motor, the 50 MHz oscillator frequency provided by the Basys-3 card is divided into lower frequencies ranging from 2 to 10 ms [1] [2]. In this case, the angle of rotation, direction and speed of the motor changes according to the position of the sun. The biggest advantage of using FPGAs instead of a discrete digital component (micro-controllers with active components) in such applications is that they are made very fast and coarse changes during design and that the whole design is achieved as a single buried system. The total programmable hardware structure (utilization of FPGA capacity) used for this project is almost 5% of the total source. All framework takes a shot at an inserted framework without a PC interface.
2018 IEEE 12th International Conference on Application of Information and Communication Technologies (AICT), 2018
Outliers in the data are very common for various fields. So filtering the data is prominent both ... more Outliers in the data are very common for various fields. So filtering the data is prominent both for computing the desired result for a data set correctly or noticing unusual behaviours. In this case study, outlier detection is used to detect false ads, which are placed in the wrong category or have the wrong values, in a real estate sale website. To accomplish this, two websites are crawled, and the real estates with the unexpectedly low or high price per meter-square value are considered as the outlier candidates. To detect outliers, five outlier detection algorithms are run separately and majority voting is used to determine the absolute result, the average price per meter-square in the location. Evaluating the results of algorithms by majority voting, enabled to tolerate deficiencies of an algorithm by others automatically with some other benefits as well.
Bu makalede i3letmede olu3turulan ham haldeki (ör. sv, xml, txt, xls, xlsx formatlar ) elektronik... more Bu makalede i3letmede olu3turulan ham haldeki (ör. sv, xml, txt, xls, xlsx formatlar ) elektronik Fatura verilerinin i3letme taraf nda i3letilmesi, yazd r lmas ve sunu u vas tas yla kar3 tarafa gönderilmesini sa§layan linux tabanl gömülü kart n tasar m ve bu sistemin aksakl §a dayan kl l § ele al nmaktad r. Bu bildiride e-Fatura ve e-Ar3iv fatura dönü3ümlerinden sorumlu olan, aksakl §a dayan kl ve da§ t k bir yap ya sahip olan gömülü DIARIST sistemi anlat lmaktad r. DIARIST sistemi kullan taraf nda bulunan, özelle3mi3 bir gömülü sistem üzerinde çal 3an, çoklu uygulamalara sahip, ar3ivleme amaçl hem uzaktaki sunu u ile etkile3imde olan ve hem de yerelde bulunan kullan (sat ) ve yaz ile haberle3en bir yap d r. DIARIST sistemleri çoklu olup, her biri do§rudan uzakta bulunan sunu u ile etkile3im halindedir. DIARIST sistemi kesintisiz hizmet vermek zorundad r: çünkü bu sistem vergi mükelle eri için mahrem olan, nansal verileri içermekte ve kullan taraf nda çal 3maktad r. Bu çal 3mada DIA...
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