PURPOSE: A method for fabricating a semiconductor substrate and a semiconductor substrate are pro... more PURPOSE: A method for fabricating a semiconductor substrate and a semiconductor substrate are provided to have improved photon / electron conversion efficiency under a short wavelength of a blue light. CONSTITUTION: A semiconductor substrate on a dielectric material includes a base layer(3), a insulating layer(5), and a first semiconductor layer having a first dopant concentration. A diffused layer is provided. The second semiconductor layer(11) has a second dopant concentration different from a first dopant concentration and includes same material as the first semiconductor layer.
Introduction of hybrid orientation substrates has led to the development of CMOS technologies in ... more Introduction of hybrid orientation substrates has led to the development of CMOS technologies in which NMOS transistors are fabricated on (100) Si and PMOS on (110) Si. This maximizes the crystal orientation dependent mobilities of electrons and holes. The Smart Cut technology has been successfully applied to fabricate hybrid orientation substrates with a buried oxide between the top Si layer and the bulk substrate having two different crystal orientations. This paper describes the application of the Smart Cut method for the fabrication of the directly (i.e. with no oxide in between) bonded 300 mm Si engineered substrates. The technological challenges, process flow and the results of the wafer characterization are presented and discussed.
2010 Proceedings of the European Solid State Device Research Conference, 2010
ABSTRACT We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture ... more ABSTRACT We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO2 gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off (ION +23% for a given IOFF =100nA/μm), and thus to obtain similar ION for n & pFETs (~650μA/μm at VDD=1V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted (Vth~+/-0.2V) for high performance (HP) CMOS with a single mid-gap metal gate.
La presente invention concerne une piece a usiner semi-conductrice comprenant un substrat 10, une... more La presente invention concerne une piece a usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie a gradient disposee sur le substrat, et au moins une couche de transition contrainte 16 a l'interieur de la partie a gradient de la couche tampon non contrainte 14, 18 et son procede de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de reduire une proportion de la courbure de la piece a usiner provoquee par la contraction du coefficient d'expansion thermique (CTE) differentiel de la couche tampon non contrainte 14, 18 par rapport a la contraction du CTE du substrat 10.
Lors de la croissance de materiaux sur substrats massifs, les parametres de maille de la couche e... more Lors de la croissance de materiaux sur substrats massifs, les parametres de maille de la couche epitaxiale et du substrat doivent etre parfaitement identiques sinon la couche se relaxe par generation de dislocations, au-dela d'une epaisseur dite epaisseur critique. La gamme de materiaux epitaxies est donc restreinte a de faibles desaccords parametriques pour eviter la degradation des performances des dispositifs optoelectroniques. La relaxation plastique des couches desaccordees peut etre limitee par la realisation de substrats deformables ou compliants qui partagent la contrainte de desaccord avec la couche epitaxiee. Un tel substrat de quelques dizaines d'angstroms doit etre transfere sur un substrat hote. Nous avons etudie deux methodes de transfert, la fusion desalignee (twist-bonding) et l'adhesion moleculaire (wafer bonding). La relaxation de la contrainte se fait, dans le premier cas, par l'intermediaire du reseau de dislocations vis de l'interface, et dan...
A quantum well thermoelectric component for use in a thermoelectric device based on the thermoele... more A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect, comprising a stack of layers of two materials respectively made on the basis of silicon and silicon-germanium, the first of the two materials, made on the basis of silicon, defining a barrier semiconductor material and the second of the two materials, made on the basis of silicon-germanium, defining a conducting semiconductor material, the barrier semiconductor material having a band gap higher than the band gap of the conducting semiconductor material, wherein the conducting semiconductor material is an alloy comprising silicon, germanium and at least a lattice-matching element, the lattice-matching element(s) being present in order to control a lattice parameter mismatch between the barrier layer made of the barrier semiconductor material and the conducting layer made of the conducting semiconductor material.
The invention concerns a process of selective transfer of labels from an initial support to a fin... more The invention concerns a process of selective transfer of labels from an initial support to a final support, each label including at least one element constituent of a microelectronic and/or optoelectronic and/or acoustic and/or mechanical device, with the elements made in a surface layer of the initial support, and the process including the following stages: a) Fixing a transfer support on the surface layer of the initial support; b) Eliminating the part of the initial support that does not correspond to the surface layer; c) Laterally defining the labels by cutting according to the thickness of the surface layer, with the cutting leaving zones to be broken off; d) Grasping one or several labels to be transferred and tearing them off by means of energy intake in the corresponding zones that can be broken off; e) Transfer and fixing the label or set of labels torn off in stage d) on the final support.
Die Erfindung betrifft ein Verfahren zur Herstellung einer Verbundstruktur (225) umfassend eine d... more Die Erfindung betrifft ein Verfahren zur Herstellung einer Verbundstruktur (225) umfassend eine durch Bestrahlung abzutrennende Schicht (215), wobei das Verfahren das Bilden eins Stapels umfasst, der Folgendes aufweist: ein Tragersubstrat (205), das aus einem Material besteht, das zumindest teilweise transparent auf einer bestimmen Wellenlange ist; eine abzutrennende Schicht (215); und eine Trennschicht (210), die zwischen dem Tragersubstrat und der abzutrennenden Schicht angeordnet ist, wobei die Trennschicht so aufgebaut ist, dass sie unter der Einwirkung von Strahlung (222a) mit einer Wellenlange, die der bestimmten Wellenlange entspricht, durch Abblattern abgetrennt werden kann, wobei das Verfahren des Weiteren wahrend des Schrittes zum Bilden des Verbundes einen Behandlungsschritt zum Modifizieren der optischen Eigenschaften der Reflexion an der Grenzflache (206) zwischen dem Tragersubstrat und der Trennschicht oder an der Oberseite (205a) des Tragersubstrats umfasst.
Silicon surface evolution during annealing was investigated by atomic force microscopy (AFM) in a... more Silicon surface evolution during annealing was investigated by atomic force microscopy (AFM) in a mixture of hydrogen (H2) and hydrogen chloride (HCl). The power spectrum density (PSD) calculated by experimental data was fitted to the analytical results of a continuum surface dynamics equation to determine the surface relaxation mechanism. The coexistence of two mechanisms was revealed, i.e., silicon surface diffusion and silicon desorption by chlorine adatoms, whose relative contribution depended on the HCl concentration. Thus, we proposed a unified model of silicon surface dynamics under pure H2 and HCl atmosphere, which sufficiently clarified the PSD evolution and allowed the determination of the diffusion and desorption reaction constants. Specifically, the evolution of the desorption reaction constant with increasing HCl concentration suggested a complex desorption path.
We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The do... more We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge conte...
PURPOSE: A method for fabricating a semiconductor substrate and a semiconductor substrate are pro... more PURPOSE: A method for fabricating a semiconductor substrate and a semiconductor substrate are provided to have improved photon / electron conversion efficiency under a short wavelength of a blue light. CONSTITUTION: A semiconductor substrate on a dielectric material includes a base layer(3), a insulating layer(5), and a first semiconductor layer having a first dopant concentration. A diffused layer is provided. The second semiconductor layer(11) has a second dopant concentration different from a first dopant concentration and includes same material as the first semiconductor layer.
Introduction of hybrid orientation substrates has led to the development of CMOS technologies in ... more Introduction of hybrid orientation substrates has led to the development of CMOS technologies in which NMOS transistors are fabricated on (100) Si and PMOS on (110) Si. This maximizes the crystal orientation dependent mobilities of electrons and holes. The Smart Cut technology has been successfully applied to fabricate hybrid orientation substrates with a buried oxide between the top Si layer and the bulk substrate having two different crystal orientations. This paper describes the application of the Smart Cut method for the fabrication of the directly (i.e. with no oxide in between) bonded 300 mm Si engineered substrates. The technological challenges, process flow and the results of the wafer characterization are presented and discussed.
2010 Proceedings of the European Solid State Device Research Conference, 2010
ABSTRACT We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture ... more ABSTRACT We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO2 gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off (ION +23% for a given IOFF =100nA/μm), and thus to obtain similar ION for n & pFETs (~650μA/μm at VDD=1V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted (Vth~+/-0.2V) for high performance (HP) CMOS with a single mid-gap metal gate.
La presente invention concerne une piece a usiner semi-conductrice comprenant un substrat 10, une... more La presente invention concerne une piece a usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie a gradient disposee sur le substrat, et au moins une couche de transition contrainte 16 a l'interieur de la partie a gradient de la couche tampon non contrainte 14, 18 et son procede de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de reduire une proportion de la courbure de la piece a usiner provoquee par la contraction du coefficient d'expansion thermique (CTE) differentiel de la couche tampon non contrainte 14, 18 par rapport a la contraction du CTE du substrat 10.
Lors de la croissance de materiaux sur substrats massifs, les parametres de maille de la couche e... more Lors de la croissance de materiaux sur substrats massifs, les parametres de maille de la couche epitaxiale et du substrat doivent etre parfaitement identiques sinon la couche se relaxe par generation de dislocations, au-dela d'une epaisseur dite epaisseur critique. La gamme de materiaux epitaxies est donc restreinte a de faibles desaccords parametriques pour eviter la degradation des performances des dispositifs optoelectroniques. La relaxation plastique des couches desaccordees peut etre limitee par la realisation de substrats deformables ou compliants qui partagent la contrainte de desaccord avec la couche epitaxiee. Un tel substrat de quelques dizaines d'angstroms doit etre transfere sur un substrat hote. Nous avons etudie deux methodes de transfert, la fusion desalignee (twist-bonding) et l'adhesion moleculaire (wafer bonding). La relaxation de la contrainte se fait, dans le premier cas, par l'intermediaire du reseau de dislocations vis de l'interface, et dan...
A quantum well thermoelectric component for use in a thermoelectric device based on the thermoele... more A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect, comprising a stack of layers of two materials respectively made on the basis of silicon and silicon-germanium, the first of the two materials, made on the basis of silicon, defining a barrier semiconductor material and the second of the two materials, made on the basis of silicon-germanium, defining a conducting semiconductor material, the barrier semiconductor material having a band gap higher than the band gap of the conducting semiconductor material, wherein the conducting semiconductor material is an alloy comprising silicon, germanium and at least a lattice-matching element, the lattice-matching element(s) being present in order to control a lattice parameter mismatch between the barrier layer made of the barrier semiconductor material and the conducting layer made of the conducting semiconductor material.
The invention concerns a process of selective transfer of labels from an initial support to a fin... more The invention concerns a process of selective transfer of labels from an initial support to a final support, each label including at least one element constituent of a microelectronic and/or optoelectronic and/or acoustic and/or mechanical device, with the elements made in a surface layer of the initial support, and the process including the following stages: a) Fixing a transfer support on the surface layer of the initial support; b) Eliminating the part of the initial support that does not correspond to the surface layer; c) Laterally defining the labels by cutting according to the thickness of the surface layer, with the cutting leaving zones to be broken off; d) Grasping one or several labels to be transferred and tearing them off by means of energy intake in the corresponding zones that can be broken off; e) Transfer and fixing the label or set of labels torn off in stage d) on the final support.
Die Erfindung betrifft ein Verfahren zur Herstellung einer Verbundstruktur (225) umfassend eine d... more Die Erfindung betrifft ein Verfahren zur Herstellung einer Verbundstruktur (225) umfassend eine durch Bestrahlung abzutrennende Schicht (215), wobei das Verfahren das Bilden eins Stapels umfasst, der Folgendes aufweist: ein Tragersubstrat (205), das aus einem Material besteht, das zumindest teilweise transparent auf einer bestimmen Wellenlange ist; eine abzutrennende Schicht (215); und eine Trennschicht (210), die zwischen dem Tragersubstrat und der abzutrennenden Schicht angeordnet ist, wobei die Trennschicht so aufgebaut ist, dass sie unter der Einwirkung von Strahlung (222a) mit einer Wellenlange, die der bestimmten Wellenlange entspricht, durch Abblattern abgetrennt werden kann, wobei das Verfahren des Weiteren wahrend des Schrittes zum Bilden des Verbundes einen Behandlungsschritt zum Modifizieren der optischen Eigenschaften der Reflexion an der Grenzflache (206) zwischen dem Tragersubstrat und der Trennschicht oder an der Oberseite (205a) des Tragersubstrats umfasst.
Silicon surface evolution during annealing was investigated by atomic force microscopy (AFM) in a... more Silicon surface evolution during annealing was investigated by atomic force microscopy (AFM) in a mixture of hydrogen (H2) and hydrogen chloride (HCl). The power spectrum density (PSD) calculated by experimental data was fitted to the analytical results of a continuum surface dynamics equation to determine the surface relaxation mechanism. The coexistence of two mechanisms was revealed, i.e., silicon surface diffusion and silicon desorption by chlorine adatoms, whose relative contribution depended on the HCl concentration. Thus, we proposed a unified model of silicon surface dynamics under pure H2 and HCl atmosphere, which sufficiently clarified the PSD evolution and allowed the determination of the diffusion and desorption reaction constants. Specifically, the evolution of the desorption reaction constant with increasing HCl concentration suggested a complex desorption path.
We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The do... more We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge conte...
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Papers by Christophe Figuet