2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
This paper explores a common-emitter buffer-based frequency multiplier which can be applied to th... more This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the phase-locked loop (PLL) to boost the overall output frequency and locking range by locking the PLL in a lower fundamental frequency and then multiplying the fundamental frequency to a higher output frequency. An integer PLL with a frequency quadrupler is designed to verify this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this D-band (110-170GHz) PLL has a wide locking range from 126.9 to 132.4GHz. The output power into a 50Ω load is -30dBm. The total power consumption is approximately 16.95mW. The PLL phase noise at 1MHz offset frequency is -66dBc/Hz. Its settling time is ~2μs. The microchip area is 850μm×760μm.
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
Advanced silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) ma... more Advanced silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) manufacturing processes require novel circuit design methodology to achieve high performance. The SiGe process leverages existing 120 nm silicon process advancements, but lower device breakdown voltages require new circuits to achieve low voltage operation. The SiGe heterojunction bipolar transistors (HBTs) with an ft over 200 GHz allow for high speed bipolar junction technology (BJT) logic blocks combined with high density and low power CMOS logic. This paper presents the design of a digital accumulator operating at 19 GHz with a 1.2 volt supply consuming only 466 mW of power. This architecture applies a modified differential pair logic family called the triple-tail cell to construct logic circuit with no stacked gates between the supplies. A folded logic technique is used to collapse logic that would normally be constructed from stacked differential pairs into parallel single stacked logic that is later recombined.
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
Wide tuning range voltage-controlled oscillators (VCO) are envisioned for applications in radars,... more Wide tuning range voltage-controlled oscillators (VCO) are envisioned for applications in radars, broadband communications, phase-locked loops and clock generation/distribution. In this paper, post-layout simulation results of a combined VCO with a ring quadrature VCO (QVCO), an exclusive-OR (XOR) and a fourth-harmonic summation block in 130nm SiGe BiCMOS technology are presented. The combined VCO can be tuned from 2.9 to 30.3GHz. At 2.9GHz, the VCO consumes 32.89mW of power and generates −56.5 dBm (2.24nW) of output power into a 50 Ohm load. At 30.3GHz, it consumes 34.2mW of power and generates −33.5 dBm (398nW) of output power. In both cases, the XOR consumes ∼25mW of power and the fourth-harmonic block consumes ∼5mW of power. The VCO phase noise at 10MHz offset frequency is −102.2dBc/Hz and −86.04dBc/Hz at 2.9GHz and 30.3GHz, respectively. The VCO figure of merit (FOM) is in the range of −136 to −141. The microchip area is 750µm×500µm. This VCO provides the widest tuning range in the 130nm ring VCOs reported till now.
ABSTRACTWe have analyzed a single-wafer chemical vapor deposition (CVD) reactor used for the sele... more ABSTRACTWe have analyzed a single-wafer chemical vapor deposition (CVD) reactor used for the selective deposition of tungsten (W) by the silanc (SiH4) reduction of tungsten hcxafluoride (WF6). Results from a reactor model, which incorporates simplified heterogeneous reaction chemistry, arc compared to experimental data obtained from the same reactor to provide insight and understanding into reactor performance and define some of the trade-offs in the design of the reactor. A reactor for this process must provide: acold-wall temperature to suppress homogeneous reactions, a uniform wafer temperature to ensure uniform stress and resistivity in deposited films, and a uniform flux of SiH4 to the wafer surface to ensure uniform thickness of films. Maintaining a small internal volume in the reaction chamber was found to be beneficial for reducing both the quantity of rcactant gas at elevated temperatures and the residence time of the gas in the reactor, both of which lead to improved selec...
International Journal of High Speed Electronics and Systems, 2004
High-speed accumulators are frequently used as a benchmark of the high-speed performance and abil... more High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011
This paper explores a common-emitter buffer-based frequency multiplier which can be applied to th... more This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the voltage-controlled oscillator (VCO) to boost the output frequency of the VCO. A VCO with a frequency quadrupler is designed and verify with this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this VCO can be tuned from 287 to 294.5GHz. The output power into a 50 Ω load is ∼ −50.9dBm. The power consumption is approximately 8.2mW. The VCO phase noise at 10MHz offset frequency is −100.7dBc/Hz. Its figure of merit (FOM) [1] is −181. Its microchip area is 550µm×500µm.
ABSTRACTThis paper reports initial results of an experimental study of the early stages of silico... more ABSTRACTThis paper reports initial results of an experimental study of the early stages of silicon thin film growth on well prepared (100) c-Si surfaces by pyrolytic deposition from silane (SiH4) during localized laser chemical vapor deposition (LLCVD). The rate of silicon thin film growth during low pressure (< 10 Torr) deposition using tightly focussed laser beams (514.5 nm, ∼ 2.5 μm FWHM) is characterized and is shown to be much slower than expected based on the previously measured silane decomposition rate. Hybrid-heating experiments, in which laser heating induces a slight temperature increase on a uniformly heated substrate in the presence of silane gas, shows that growth is inhibited within the laser irradiation region. This result suggests that a nonpyrolytic mechanism contributes to silicon growth in laser CVD. Possible explanations for this nonpyrolytic growth mechanism are discussed.
ABSTRACTHafnium oxide is a promising dielectric for future microelectronic applications. HfO2 thi... more ABSTRACTHafnium oxide is a promising dielectric for future microelectronic applications. HfO2 thin films (10–75nm) were deposited on Pt/SiO2/Si and quartz substrates by Pulsed DC magnetron reactive sputtering. Top electrodes of Pt were formed by e-beam evaporation through an aperture mask on the HfO2/Pt/SiO2/Si samples to create MIM capacitors. Various process conditions (Ar/O2 ratio, DC power, and deposition rate) and post-deposition annealing conditions (time and temperature) were investigated. The structure of the HfO2 films was characterized by X-ray diffraction (XRD) and the roughness was measured by a profilometer. The electrical properties were characterized in terms of their relative permittivity (εr(T) and εr(f)), and leakage behavior (I-V and I-t). The electrical measurements were performed over a temperature range from –5 to 200°C. For the best samples, the relative permittivity of HfO2 was found to be ∼27 after anneal and increased by 0.027%/°C with increasing temperatur...
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications.... more Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications. This paper presents the architecture of an Impulse Radio Ultra Wide Band (IR-UWB) transmitter for outdoor communications which complies with the FCC spectral limits. The transmitter consists of a pulse generator (PG) and a deriver circuit and has an operating frequency between 3.1 GHz and 6.4 GHz. The pulse output amplitude is ~ 700mV peak-to-peak into a 50Ω resistive load. The maximum data rate that can be achieved by the transmitter is 250Mbps at an overall power efficiency of 6.3%. The transmitter is compensated for voltage and temperature (VT) variations. The output pulse energy changes by less than 24% as the temperature varies from -55°C to 100°C, and by less than 5% as the supply voltage varies between 2.3 and 3.6V. The design is implemented in 180nm CMOS process and the simulation results with extracted R, L, C parasitics are presented.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
This paper explores a common-emitter buffer-based frequency multiplier which can be applied to th... more This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the phase-locked loop (PLL) to boost the overall output frequency and locking range by locking the PLL in a lower fundamental frequency and then multiplying the fundamental frequency to a higher output frequency. An integer PLL with a frequency quadrupler is designed to verify this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this D-band (110-170GHz) PLL has a wide locking range from 126.9 to 132.4GHz. The output power into a 50Ω load is -30dBm. The total power consumption is approximately 16.95mW. The PLL phase noise at 1MHz offset frequency is -66dBc/Hz. Its settling time is ~2μs. The microchip area is 850μm×760μm.
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
Advanced silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) ma... more Advanced silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) manufacturing processes require novel circuit design methodology to achieve high performance. The SiGe process leverages existing 120 nm silicon process advancements, but lower device breakdown voltages require new circuits to achieve low voltage operation. The SiGe heterojunction bipolar transistors (HBTs) with an ft over 200 GHz allow for high speed bipolar junction technology (BJT) logic blocks combined with high density and low power CMOS logic. This paper presents the design of a digital accumulator operating at 19 GHz with a 1.2 volt supply consuming only 466 mW of power. This architecture applies a modified differential pair logic family called the triple-tail cell to construct logic circuit with no stacked gates between the supplies. A folded logic technique is used to collapse logic that would normally be constructed from stacked differential pairs into parallel single stacked logic that is later recombined.
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
Wide tuning range voltage-controlled oscillators (VCO) are envisioned for applications in radars,... more Wide tuning range voltage-controlled oscillators (VCO) are envisioned for applications in radars, broadband communications, phase-locked loops and clock generation/distribution. In this paper, post-layout simulation results of a combined VCO with a ring quadrature VCO (QVCO), an exclusive-OR (XOR) and a fourth-harmonic summation block in 130nm SiGe BiCMOS technology are presented. The combined VCO can be tuned from 2.9 to 30.3GHz. At 2.9GHz, the VCO consumes 32.89mW of power and generates −56.5 dBm (2.24nW) of output power into a 50 Ohm load. At 30.3GHz, it consumes 34.2mW of power and generates −33.5 dBm (398nW) of output power. In both cases, the XOR consumes ∼25mW of power and the fourth-harmonic block consumes ∼5mW of power. The VCO phase noise at 10MHz offset frequency is −102.2dBc/Hz and −86.04dBc/Hz at 2.9GHz and 30.3GHz, respectively. The VCO figure of merit (FOM) is in the range of −136 to −141. The microchip area is 750µm×500µm. This VCO provides the widest tuning range in the 130nm ring VCOs reported till now.
ABSTRACTWe have analyzed a single-wafer chemical vapor deposition (CVD) reactor used for the sele... more ABSTRACTWe have analyzed a single-wafer chemical vapor deposition (CVD) reactor used for the selective deposition of tungsten (W) by the silanc (SiH4) reduction of tungsten hcxafluoride (WF6). Results from a reactor model, which incorporates simplified heterogeneous reaction chemistry, arc compared to experimental data obtained from the same reactor to provide insight and understanding into reactor performance and define some of the trade-offs in the design of the reactor. A reactor for this process must provide: acold-wall temperature to suppress homogeneous reactions, a uniform wafer temperature to ensure uniform stress and resistivity in deposited films, and a uniform flux of SiH4 to the wafer surface to ensure uniform thickness of films. Maintaining a small internal volume in the reaction chamber was found to be beneficial for reducing both the quantity of rcactant gas at elevated temperatures and the residence time of the gas in the reactor, both of which lead to improved selec...
International Journal of High Speed Electronics and Systems, 2004
High-speed accumulators are frequently used as a benchmark of the high-speed performance and abil... more High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011
This paper explores a common-emitter buffer-based frequency multiplier which can be applied to th... more This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the voltage-controlled oscillator (VCO) to boost the output frequency of the VCO. A VCO with a frequency quadrupler is designed and verify with this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this VCO can be tuned from 287 to 294.5GHz. The output power into a 50 Ω load is ∼ −50.9dBm. The power consumption is approximately 8.2mW. The VCO phase noise at 10MHz offset frequency is −100.7dBc/Hz. Its figure of merit (FOM) [1] is −181. Its microchip area is 550µm×500µm.
ABSTRACTThis paper reports initial results of an experimental study of the early stages of silico... more ABSTRACTThis paper reports initial results of an experimental study of the early stages of silicon thin film growth on well prepared (100) c-Si surfaces by pyrolytic deposition from silane (SiH4) during localized laser chemical vapor deposition (LLCVD). The rate of silicon thin film growth during low pressure (< 10 Torr) deposition using tightly focussed laser beams (514.5 nm, ∼ 2.5 μm FWHM) is characterized and is shown to be much slower than expected based on the previously measured silane decomposition rate. Hybrid-heating experiments, in which laser heating induces a slight temperature increase on a uniformly heated substrate in the presence of silane gas, shows that growth is inhibited within the laser irradiation region. This result suggests that a nonpyrolytic mechanism contributes to silicon growth in laser CVD. Possible explanations for this nonpyrolytic growth mechanism are discussed.
ABSTRACTHafnium oxide is a promising dielectric for future microelectronic applications. HfO2 thi... more ABSTRACTHafnium oxide is a promising dielectric for future microelectronic applications. HfO2 thin films (10–75nm) were deposited on Pt/SiO2/Si and quartz substrates by Pulsed DC magnetron reactive sputtering. Top electrodes of Pt were formed by e-beam evaporation through an aperture mask on the HfO2/Pt/SiO2/Si samples to create MIM capacitors. Various process conditions (Ar/O2 ratio, DC power, and deposition rate) and post-deposition annealing conditions (time and temperature) were investigated. The structure of the HfO2 films was characterized by X-ray diffraction (XRD) and the roughness was measured by a profilometer. The electrical properties were characterized in terms of their relative permittivity (εr(T) and εr(f)), and leakage behavior (I-V and I-t). The electrical measurements were performed over a temperature range from –5 to 200°C. For the best samples, the relative permittivity of HfO2 was found to be ∼27 after anneal and increased by 0.027%/°C with increasing temperatur...
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications.... more Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications. This paper presents the architecture of an Impulse Radio Ultra Wide Band (IR-UWB) transmitter for outdoor communications which complies with the FCC spectral limits. The transmitter consists of a pulse generator (PG) and a deriver circuit and has an operating frequency between 3.1 GHz and 6.4 GHz. The pulse output amplitude is ~ 700mV peak-to-peak into a 50Ω resistive load. The maximum data rate that can be achieved by the transmitter is 250Mbps at an overall power efficiency of 6.3%. The transmitter is compensated for voltage and temperature (VT) variations. The output pulse energy changes by less than 24% as the temperature varies from -55°C to 100°C, and by less than 5% as the supply voltage varies between 2.3 and 3.6V. The design is implemented in 180nm CMOS process and the simulation results with extracted R, L, C parasitics are presented.
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Papers by David Kotecki