2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014
This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic trans... more This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic transformers on silicon substrates. R, L Foster networks in a T-topology are used to capture the frequency-dependent proximity and skin effects in the transformer windings as well as substrate eddy-current effects and, hence, the complete frequency-dependent self and mutual impedances of the transformer. The model is passive by construction and is compatible with transient simulations. A stacked transformer on a 10 ohm-centimeter CMOS substrate has been used to verify the model. The model exhibits good agreement with simulation data and measurements over a frequency range of 0.1 - 10 GHz.
Abstract-This paper presents a novel analytical closed form expression for the crosstalk noise vo... more Abstract-This paper presents a novel analytical closed form expression for the crosstalk noise voltage and delay in the presence of skin effect. With the rapid development of high frequency IC technology, a number of high-speed interconnect effects, such as ringing, signal delay, distortion, reflections, and crosstalk, need to be considered during the IC design. Skin effect is one of the high frequency phenomena that can adversely affect the distribution of current density in interconnect because the problem associated with the ...
2010 International Conference on Signal and Image Processing, 2010
Abstract Earlier only the delay caused due to the presence of gates was considered to be an impor... more Abstract Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity, on-chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. In this paper, we have obtained an analytical delay model, for RLCG interconnect lines, that in addition to preserving the effectiveness of the previous RLC interconnect models, improves the accuracy for deep submicron technologies that are used at higher ...
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014
This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic trans... more This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic transformers on silicon substrates. R, L Foster networks in a T-topology are used to capture the frequency-dependent proximity and skin effects in the transformer windings as well as substrate eddy-current effects and, hence, the complete frequency-dependent self and mutual impedances of the transformer. The model is passive by construction and is compatible with transient simulations. A stacked transformer on a 10 ohm-centimeter CMOS substrate has been used to verify the model. The model exhibits good agreement with simulation data and measurements over a frequency range of 0.1 - 10 GHz.
Abstract-This paper presents a novel analytical closed form expression for the crosstalk noise vo... more Abstract-This paper presents a novel analytical closed form expression for the crosstalk noise voltage and delay in the presence of skin effect. With the rapid development of high frequency IC technology, a number of high-speed interconnect effects, such as ringing, signal delay, distortion, reflections, and crosstalk, need to be considered during the IC design. Skin effect is one of the high frequency phenomena that can adversely affect the distribution of current density in interconnect because the problem associated with the ...
2010 International Conference on Signal and Image Processing, 2010
Abstract Earlier only the delay caused due to the presence of gates was considered to be an impor... more Abstract Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity, on-chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. In this paper, we have obtained an analytical delay model, for RLCG interconnect lines, that in addition to preserving the effectiveness of the previous RLC interconnect models, improves the accuracy for deep submicron technologies that are used at higher ...
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Papers by Dyuti Sengupta