Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates... more Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.
2018 18th International Workshop on Junction Technology (IWJT), 2018
In this paper, we present a short overview of the CMOS-compatible contact technology developed in... more In this paper, we present a short overview of the CMOS-compatible contact technology developed in our group on n-InP and p-InGaAs for Si photonic applications. Obtained results cover a wide spectrum: from surface preparation and solid-state reaction to electrical results and laser integration. The metallurgy of several systems including Ni / InGaAs, Ni / InP, Ti / InGaAs and Ti / InP has been studied. Most of the metallizations studied provide efficient solutions for contacting n-InP and p-InGaAs. Finally, guidelines for integrating low resistivity contacts are proposed.
2018 22nd International Conference on Ion Implantation Technology (IIT), 2018
The impact of the amorphous silicon (a-Si) thickness generated by the Pre-Amorphization Implantat... more The impact of the amorphous silicon (a-Si) thickness generated by the Pre-Amorphization Implantation (PAI) process and the potential benefits of adding a carbon implantation step on the Ni-silicidation process was evaluated. The silicide resistivity is improved in the same way when Si or Ge PAI process is performed compared to the reference sample. However, the specie used for PAI has an impact on the silicide roughness. Adding carbon after Ge or Si implantation reduces the silicide roughness at the expense of an increased resistivity. It has also a positive impact on the Pt distribution in the silicide and its thermal stability.
2019 19th International Workshop on Junction Technology (IWJT), 2019
Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recen... more Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recently, in order to meet performance requirements in advanced digital nodes, process integration have consensually shifted towards NiPt-based silicides [1] . Nevertheless, advanced memory and imaging technologies being still based on 90-nm core MOS, developments and studies on CoSi 2 silicide are still of the best interest as new challenges are emerging.
Depuis les annees 2000, en raison d’une multitude de moyens de communication emergents, les besoi... more Depuis les annees 2000, en raison d’une multitude de moyens de communication emergents, les besoins en termes d’echange de donnees n’ont cesse d’augmenter. Ces modifications ont conduit a l’initiation d’une transition depuis les technologies electroniques vers les technologies et interconnexions optiques. Entre autres, ces nouvelles technologies necessitent l’utilisation de composants emetteurs et recepteurs de photons constitues de materiaux III-V. De facon a miniaturiser ces composants et a augmenter leurs performances tout en diminuant leur cout de fabrication, un modele d’integration innovant consiste a integrer directement les sources III-V sur le circuit photonique silicium 200 mm. Afin d’optimiser les performances du laser III-V tout en respectant les contraintes liees a une salle blanche front-end / middle-end silicium, la realisation d’une telle integration necessite notamment le developpement de contacts innovants sur n-InP et p-InGaAs.Ces travaux de these sont ainsi centr...
Silicon photonic platforms are becoming more and more mature with competitive devices suitable fo... more Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid. In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for...
In this progress review, an overview of the CMOS-compatible contact technology developed at the C... more In this progress review, an overview of the CMOS-compatible contact technology developed at the CEA-Leti for Si photonics applications is proposed. The elaboration of III–V/Si hybrid lasers implies the development of ohmic contacts on n-InP and p-InGaAs III–V materials. In this way, a contact technology fully compatible with a Si-Fab line was developed. The results presented in this manuscript cover a wide scope: from surface preparation and solid-state reaction to electrical results and integration guidelines. The metallurgy of several systems including Ni/InGaAs, Ni/InP, Ti/InGaAs and Ti/InP was studied. The direct metallization of III–V materials using Ni2P was also introduced. Most of the studied metallizations provided efficient solutions for achieving ohmic contacts on n-InP and p-InGaAs. Finally, the contact technology developed in the framework of this study was successfully integrated on 200 mm CMOS-compatible III–V/Si hybrid lasers.
Abstract Silicon photonics has generated an amazing interest for many years to address the challe... more Abstract Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.
In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metalliz... more In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni<sub>2</sub>P metallization combined with an <italic>in situ</italic> Ar<sup>+</sup> preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as <inline-formula> <tex-math notation="LaTeX">$4.3 \times 10^{-6}~\Omega ^{2}$ </tex-math></inline-formula> on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.
InGaAs and InP layers were treated by using Ar and He direct plasmas coupled with wet chemical tr... more InGaAs and InP layers were treated by using Ar and He direct plasmas coupled with wet chemical treatments. InP surfaces are more sensitive to the various treatments than the InGaAs ones. Suitable and efficient treatments have been proposed to offer a good compromise between impact on surface and native oxide removal. We have demonstrated that concentrated HCl solution cleanings followed by He direct plasma treatment are efficient for the removal of InGaAs native oxides whereas He plasma exposure combined to a diluted HCl solution cleaning is more suitable for InP surfaces.
Integrated Photonics Platforms: Fundamental Research, Manufacturing and Applications, 2020
We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to... more We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates... more Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.
2018 18th International Workshop on Junction Technology (IWJT), 2018
In this paper, we present a short overview of the CMOS-compatible contact technology developed in... more In this paper, we present a short overview of the CMOS-compatible contact technology developed in our group on n-InP and p-InGaAs for Si photonic applications. Obtained results cover a wide spectrum: from surface preparation and solid-state reaction to electrical results and laser integration. The metallurgy of several systems including Ni / InGaAs, Ni / InP, Ti / InGaAs and Ti / InP has been studied. Most of the metallizations studied provide efficient solutions for contacting n-InP and p-InGaAs. Finally, guidelines for integrating low resistivity contacts are proposed.
2018 22nd International Conference on Ion Implantation Technology (IIT), 2018
The impact of the amorphous silicon (a-Si) thickness generated by the Pre-Amorphization Implantat... more The impact of the amorphous silicon (a-Si) thickness generated by the Pre-Amorphization Implantation (PAI) process and the potential benefits of adding a carbon implantation step on the Ni-silicidation process was evaluated. The silicide resistivity is improved in the same way when Si or Ge PAI process is performed compared to the reference sample. However, the specie used for PAI has an impact on the silicide roughness. Adding carbon after Ge or Si implantation reduces the silicide roughness at the expense of an increased resistivity. It has also a positive impact on the Pt distribution in the silicide and its thermal stability.
2019 19th International Workshop on Junction Technology (IWJT), 2019
Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recen... more Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recently, in order to meet performance requirements in advanced digital nodes, process integration have consensually shifted towards NiPt-based silicides [1] . Nevertheless, advanced memory and imaging technologies being still based on 90-nm core MOS, developments and studies on CoSi 2 silicide are still of the best interest as new challenges are emerging.
Depuis les annees 2000, en raison d’une multitude de moyens de communication emergents, les besoi... more Depuis les annees 2000, en raison d’une multitude de moyens de communication emergents, les besoins en termes d’echange de donnees n’ont cesse d’augmenter. Ces modifications ont conduit a l’initiation d’une transition depuis les technologies electroniques vers les technologies et interconnexions optiques. Entre autres, ces nouvelles technologies necessitent l’utilisation de composants emetteurs et recepteurs de photons constitues de materiaux III-V. De facon a miniaturiser ces composants et a augmenter leurs performances tout en diminuant leur cout de fabrication, un modele d’integration innovant consiste a integrer directement les sources III-V sur le circuit photonique silicium 200 mm. Afin d’optimiser les performances du laser III-V tout en respectant les contraintes liees a une salle blanche front-end / middle-end silicium, la realisation d’une telle integration necessite notamment le developpement de contacts innovants sur n-InP et p-InGaAs.Ces travaux de these sont ainsi centr...
Silicon photonic platforms are becoming more and more mature with competitive devices suitable fo... more Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid. In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for...
In this progress review, an overview of the CMOS-compatible contact technology developed at the C... more In this progress review, an overview of the CMOS-compatible contact technology developed at the CEA-Leti for Si photonics applications is proposed. The elaboration of III–V/Si hybrid lasers implies the development of ohmic contacts on n-InP and p-InGaAs III–V materials. In this way, a contact technology fully compatible with a Si-Fab line was developed. The results presented in this manuscript cover a wide scope: from surface preparation and solid-state reaction to electrical results and integration guidelines. The metallurgy of several systems including Ni/InGaAs, Ni/InP, Ti/InGaAs and Ti/InP was studied. The direct metallization of III–V materials using Ni2P was also introduced. Most of the studied metallizations provided efficient solutions for achieving ohmic contacts on n-InP and p-InGaAs. Finally, the contact technology developed in the framework of this study was successfully integrated on 200 mm CMOS-compatible III–V/Si hybrid lasers.
Abstract Silicon photonics has generated an amazing interest for many years to address the challe... more Abstract Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.
In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metalliz... more In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni<sub>2</sub>P metallization combined with an <italic>in situ</italic> Ar<sup>+</sup> preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as <inline-formula> <tex-math notation="LaTeX">$4.3 \times 10^{-6}~\Omega ^{2}$ </tex-math></inline-formula> on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.
InGaAs and InP layers were treated by using Ar and He direct plasmas coupled with wet chemical tr... more InGaAs and InP layers were treated by using Ar and He direct plasmas coupled with wet chemical treatments. InP surfaces are more sensitive to the various treatments than the InGaAs ones. Suitable and efficient treatments have been proposed to offer a good compromise between impact on surface and native oxide removal. We have demonstrated that concentrated HCl solution cleanings followed by He direct plasma treatment are efficient for the removal of InGaAs native oxides whereas He plasma exposure combined to a diluted HCl solution cleaning is more suitable for InP surfaces.
Integrated Photonics Platforms: Fundamental Research, Manufacturing and Applications, 2020
We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to... more We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
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Papers by Elodie GHEGIN