IEEE International Integrated Reliability Workshop Final Report, 2004
Fast electron trapping in the high-k gate dielectrics is shown to effectively increase the magnit... more Fast electron trapping in the high-k gate dielectrics is shown to effectively increase the magnitude of the threshold voltage during the DC measurements of the drain current, which leads to underestimation of the intrinsic channel carrier mobility. An approach based on the pulse Id-Vg technique is proposed to estimate a correction factor to the DC mobility.
Hafnium dioxide or hafnia is a wide band gap dielectric used in a range of electronic application... more Hafnium dioxide or hafnia is a wide band gap dielectric used in a range of electronic applications from field effect transistors to resistive memory. In many of these applications, it is important to maintain control over oxygen stoichiometry, which can be realized in practice by using a metal layer, specifically hafnium, to getter oxygen from the adjacent dielectric. In this paper, we employ density functional theory to study the thermodynamic stability of an interface between (100)-oriented monoclinic hafnia and hafnium metal. The nudged elastic band method is used to calculate the energy barrier for migration of oxygen from the oxide to the metal. Our investigation shows that the presence of hafnium lowers the formation energy of oxygen vacancies in hafnia, but more importantly the oxidation of hafnium through the migration of oxygen from hafnia is favored energetically.
Frontiers in Electronics - Proceedings of the WOFE-04, 2006
Relations between the electronic properties of high-k materials and electrical characteristics of... more Relations between the electronic properties of high-k materials and electrical characteristics of high-k transistor are discussed. It is pointed out that the intrinsic limitations of these materials from the standpoint of gate dielectric applications are related to the presence of d-electrons, which facilitate high values of the dielectric constant. It is shown that the presence of structural defects responsible for electron trapping and fixed charges, and the dielectrics' tendency for crystallization and phase separation induce threshold voltage instability and mobility degradation in high-k transistors. The quality of the SiO 2-like layer at the high-k/ Si substrate interface, as well as dielectric interaction with the gate electrode, may significantly affect device characteristics.
Hafnium dioxide currently is considered a dielectric of choice for novel MOSFET devices but it ha... more Hafnium dioxide currently is considered a dielectric of choice for novel MOSFET devices but it has an important drawback (as most high-k films on silicon) of low crystallization temperature. We use large scale plane wave density functional simulations of the HfO2/SiOx/Si system to determine the properties of the amorphous hafnia films and the mechanisms of their crystallization and defects formation
2006 International Symposium on VLSI Technology, Systems, and Applications, 2006
The results in this paper suggest that migration of the electrons, captured during the fast charg... more The results in this paper suggest that migration of the electrons, captured during the fast charging process, to other available traps represents the major process responsible for the intrinsic Vt instability in the high-k NMOS transistors. The extracted trap characteristics are consistent with those of the oxygen vacancies in the monoclinic hafnia
We suggest that the polaronic trapping of electrons is possible in the high-k dielectrics alongsi... more We suggest that the polaronic trapping of electrons is possible in the high-k dielectrics alongside with the commonly discussed Poole-Frankel resonant tunneling process or recapture of the electrons from the conduction band onto pre- existed defect states. The main feature of this mechanism is the charge self-trapping, i.e. formation of a localized defect state as a result of the electron-lattice interaction. We consider the charge trapping properties of single oxygen vacancies and di-vacancies in the m-HfO2 as well as the various models for oxygen deficient and stoichiometric disordered hafnia. We find evidence of polaronic trapping in all these systems, which may indicate its universality in high- k materials.
2008 IEEE International Reliability Physics Symposium, 2008
ABSTRACT Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transco... more ABSTRACT Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed for various device parameters. This plasma damage can deteriorate the reliability of sub 32 nm metal gate/high-k dielectric CMOSFETs.
Advances in Resist Technology and Processing XVII, 2000
As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requi... more As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requirements approaching 50 nm. Overlay specifications are typically 30% of critical dimension (CD), 45 nm maximum error for 150 nm geometries, but even non-critical layers at quarter micron may ...
In this paper, reliability as well as electrical properties of high capacitance density metal–ins... more In this paper, reliability as well as electrical properties of high capacitance density metal–insulator–metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1nA/cm2 at room temperature and 1V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.
Phase transitions induced by the quenching of reorientations in a system of impurity centres with... more Phase transitions induced by the quenching of reorientations in a system of impurity centres with adiabatic potentials having several equivalent minima are discussed. In addition to inter-centre coupling the transition temperature depends on the interaction between the impurity and the crystal. The interaction of the impurity electronic states with the crystalline vibration causing the formation of the minima of the
IEEE International Integrated Reliability Workshop Final Report, 2004
Fast electron trapping in the high-k gate dielectrics is shown to effectively increase the magnit... more Fast electron trapping in the high-k gate dielectrics is shown to effectively increase the magnitude of the threshold voltage during the DC measurements of the drain current, which leads to underestimation of the intrinsic channel carrier mobility. An approach based on the pulse Id-Vg technique is proposed to estimate a correction factor to the DC mobility.
Hafnium dioxide or hafnia is a wide band gap dielectric used in a range of electronic application... more Hafnium dioxide or hafnia is a wide band gap dielectric used in a range of electronic applications from field effect transistors to resistive memory. In many of these applications, it is important to maintain control over oxygen stoichiometry, which can be realized in practice by using a metal layer, specifically hafnium, to getter oxygen from the adjacent dielectric. In this paper, we employ density functional theory to study the thermodynamic stability of an interface between (100)-oriented monoclinic hafnia and hafnium metal. The nudged elastic band method is used to calculate the energy barrier for migration of oxygen from the oxide to the metal. Our investigation shows that the presence of hafnium lowers the formation energy of oxygen vacancies in hafnia, but more importantly the oxidation of hafnium through the migration of oxygen from hafnia is favored energetically.
Frontiers in Electronics - Proceedings of the WOFE-04, 2006
Relations between the electronic properties of high-k materials and electrical characteristics of... more Relations between the electronic properties of high-k materials and electrical characteristics of high-k transistor are discussed. It is pointed out that the intrinsic limitations of these materials from the standpoint of gate dielectric applications are related to the presence of d-electrons, which facilitate high values of the dielectric constant. It is shown that the presence of structural defects responsible for electron trapping and fixed charges, and the dielectrics' tendency for crystallization and phase separation induce threshold voltage instability and mobility degradation in high-k transistors. The quality of the SiO 2-like layer at the high-k/ Si substrate interface, as well as dielectric interaction with the gate electrode, may significantly affect device characteristics.
Hafnium dioxide currently is considered a dielectric of choice for novel MOSFET devices but it ha... more Hafnium dioxide currently is considered a dielectric of choice for novel MOSFET devices but it has an important drawback (as most high-k films on silicon) of low crystallization temperature. We use large scale plane wave density functional simulations of the HfO2/SiOx/Si system to determine the properties of the amorphous hafnia films and the mechanisms of their crystallization and defects formation
2006 International Symposium on VLSI Technology, Systems, and Applications, 2006
The results in this paper suggest that migration of the electrons, captured during the fast charg... more The results in this paper suggest that migration of the electrons, captured during the fast charging process, to other available traps represents the major process responsible for the intrinsic Vt instability in the high-k NMOS transistors. The extracted trap characteristics are consistent with those of the oxygen vacancies in the monoclinic hafnia
We suggest that the polaronic trapping of electrons is possible in the high-k dielectrics alongsi... more We suggest that the polaronic trapping of electrons is possible in the high-k dielectrics alongside with the commonly discussed Poole-Frankel resonant tunneling process or recapture of the electrons from the conduction band onto pre- existed defect states. The main feature of this mechanism is the charge self-trapping, i.e. formation of a localized defect state as a result of the electron-lattice interaction. We consider the charge trapping properties of single oxygen vacancies and di-vacancies in the m-HfO2 as well as the various models for oxygen deficient and stoichiometric disordered hafnia. We find evidence of polaronic trapping in all these systems, which may indicate its universality in high- k materials.
2008 IEEE International Reliability Physics Symposium, 2008
ABSTRACT Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transco... more ABSTRACT Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed for various device parameters. This plasma damage can deteriorate the reliability of sub 32 nm metal gate/high-k dielectric CMOSFETs.
Advances in Resist Technology and Processing XVII, 2000
As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requi... more As design rules dip below 180 nm, DUV scanners are used at all critical levels with overlay requirements approaching 50 nm. Overlay specifications are typically 30% of critical dimension (CD), 45 nm maximum error for 150 nm geometries, but even non-critical layers at quarter micron may ...
In this paper, reliability as well as electrical properties of high capacitance density metal–ins... more In this paper, reliability as well as electrical properties of high capacitance density metal–insulator–metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1nA/cm2 at room temperature and 1V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.
Phase transitions induced by the quenching of reorientations in a system of impurity centres with... more Phase transitions induced by the quenching of reorientations in a system of impurity centres with adiabatic potentials having several equivalent minima are discussed. In addition to inter-centre coupling the transition temperature depends on the interaction between the impurity and the crystal. The interaction of the impurity electronic states with the crystalline vibration causing the formation of the minima of the
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