The paper presents a new analytical method for extracting the diode ideality factor of a p-n junc... more The paper presents a new analytical method for extracting the diode ideality factor of a p-n junction device using Lambert W-function model and the dark current-voltage data. The extracted values are found to be in good agreement with those calculated experimentally from dark current-voltage charac-teristics. Key Words: Ideality factor; Lambert W-function; Solar cell. 1.
The dark alternating current (ac) parameters of commercially available silicon p-i-n-photodiodes ... more The dark alternating current (ac) parameters of commercially available silicon p-i-n-photodiodes are measured and compared at room temperature both in forward and reverse bias using the impedance spectroscopy technique. The ac behavior of the photodiodes is found to be almost the same. For bias voltages in the range from −0.8 to 0.0 V, the typical photodiode behaves like a pure
The effects of post-deposition processes such as 0268-1242/12/5/014/img1 dip and/or annealing in ... more The effects of post-deposition processes such as 0268-1242/12/5/014/img1 dip and/or annealing in air on the material and device properties of vacuum-evaporated Au-CdTe/CdS-TO heterojunction solar cells have been investigated. The 0268-1242/12/5/014/img2 dip followed by air annealing at 0268-1242/12/5/014/img3 for 5 min improved the device efficiency significantly, resulting in decreased CdTe resistivity and enhanced grain size. The temperature-dependent current - voltage analysis indicated that above 280 K interface recombination dominates the current transport mechanism for the as-grown samples, while depletion region recombination starts to be dominant after annealing the samples with 0268-1242/12/5/014/img2. Below 280 K multistep tunnelling is identified to be the dominant transport mechanism. Frequency-dependent capacitance - voltage studies revealed that after annealing with 0268-1242/12/5/014/img2 the density of interface states decreases and the quality of the heterointerface improves. The capacitance of the CdS/CdTe heterojunctions has been analysed using a model based on the existence of a single dominant trap level, identified at 0.40 eV above the valence band with a concentration of 0268-1242/12/5/014/img6.
CdTe;CdS thin lms and n CdS=p CdTe heterostructures have been prepared by conventional vacuum eva... more CdTe;CdS thin lms and n CdS=p CdTe heterostructures have been prepared by conventional vacuum evaporation technique. Some post deposition treatments to optimize the device eciency have been analyzed and the eects of the individual process steps on the material and device properties were investigated. Annealing in air with and without CdCl2 -treatment decreased the CdTe resistivity. The CdCl2 -dip followed by annealing in air at 300C for 5 min improved the grain size and polycrystalline nature of CdTe thin lms. Solar eciency improvements were achieved when heterojunctions were prepared on successively treated (i.e. etched, air annealed, CdCl2 -processed) CdTe surfaces. Etching of the CdTe surface with potassium dichromate solution prior to metal contact deposition lead to the formation of low-resistance Au contacts and increase in open circuit voltage and ll factor values.
Measurements of the dark reverse current in a typical BPW34 silicon photodiode have been made in ... more Measurements of the dark reverse current in a typical BPW34 silicon photodiode have been made in the temperature range 100{300 K at various reverse bias voltages ranging from 0 to 60 V. Various transport models have been applied to analyze the temperature dependence of the reverse current-voltage data. We suggest that Bardeen’s model for a modied Schottky-like interfacial junction, that takes into account the eect of interfacial localized states, can be satisfactorily applied to describe the reverse current-voltage characteristics at bias voltages below 50 V.
This article presents a study on the energy distribution of defects in efficient thin film ZnO/Cd... more This article presents a study on the energy distribution of defects in efficient thin film ZnO/CdS/Cu(In,Ga)Se2 heterojunction solar cell by the use of admittance spectroscopy. The capacitance spectra of the device has been analyzed using a model based on the existence of a homogeneous distribution of bulk acceptors in the absorber Cu(In,Ga)Se2 layer. This model reveals an emission from a distribution of hole traps centered at an activation energy of about 300 meV with a defect density of 1.2 \times 1017 eV-1 cm-3. The band gap of the absorber layer is estimated to be about 1.46 eV which corresponds to a Ga content of about x \approx 0.7 with x the ratio Ga/(Ga+In).
The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunc... more The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunction solar cells for temperatures below 300~K was investigated. The current-voltage properties of these solar cells is explained via tunnelling enhanced bulk and interface recombination models which give a quantitative description of the electronic loss mechanisms in the chalcopyrite-based heterojunction solar cells. The temperature dependence of the saturation current and the diode ideality factors of the as-grown and CdCl2 processed CdTe solar cells are shown to be well described by this model.
The paper presents a new analytical method for extracting the diode ideality factor of a p-n junc... more The paper presents a new analytical method for extracting the diode ideality factor of a p-n junction device using Lambert W-function model and the dark current-voltage data. The extracted values are found to be in good agreement with those calculated experimentally from dark current-voltage characteristics.
Forward bias recombination (current transport) mechanisms have been evaluated for thin film solar... more Forward bias recombination (current transport) mechanisms have been evaluated for thin film solar cells and correlated to the in-gap trap levels present. Here CdTe/CdS devices were chosen as an archetypal example of a modern thin film solar cell, and a set of devices with a range of design variables was used in order to reveal the full range of behaviours that may operate to limit current transport. Experimental current–voltage–temperature datasets were compared to mathematical models of transport, and the in-gap traps were evaluated by thermal admittance spectroscopy. The current transport mechanisms operating are presented on a temperature–voltage diagram. Three regimes were identified: at 'intermediate' voltages, the behaviour was temperature dependent. From 300 K down to 240 K, thermally activated Shockley Read Hall recombination mediated by a 0.38 eV trap (V Cd) dominated the transport. Between 200 and 240 K the transport was thermally activated but below 200 K the mechanism became dominated by tunnel assisted interface recombination. At 'low' voltages (and for all devices at all voltages when measured at T < 200 K) band to band recombination is via multi-step tunnelling through in-gap states. At high voltage, the forward current is dominated by the well-known limiting effect of the back Schottky contact to the CdTe which is in reverse bias. The current transport behaviour is also correlated with the n-CdS thickness and CdCl2 processing conditions, both of which are critical to device performance.
A simple approach, which can estimate the barrier height of non-Ohmic back contacts for CdS/CdTe ... more A simple approach, which can estimate the barrier height of non-Ohmic back contacts for CdS/CdTe solar cell by using its temperature dependent forward biased current-voltage data, is explained. The method involves modelling the forward J–V characteristics using a double exponential expression for the main junction and by a reverse biased Schottky barrier for the back contact. Cells processed with both CdCl2 and MgCl2 are compared, with the current transport phenomena in both kinds of cells also being analysed. Performance loss due to limitation of the forward bias hole current, and its dependence on the post-deposition chloride processing, is discussed. The forward current transport is mainly dominated by recombination at CdS/CdTe interfacial region with pronounced tunnelling effects. Classical Schottky-type conduction, as described by the Richardson-Schottky formula, is a good fit to the reverse biased current-voltage behaviour of an Au/CdTe junction above ∼240 K. Below this temperature, the current limiting effect due to the increasing contribution from interfacial defect states can be satisfactorily explained by Bardeen’s model for a modified Schottky type barrier at back contact interface.
Abstract A simple approach, which can estimate the diode ideality factor of a high efficiency pn ... more Abstract A simple approach, which can estimate the diode ideality factor of a high efficiency pn junction solar cell under illumination by using its current–voltage data, is explained. We have proposed that an analytical method based on Lambert W-function is sufficient for the extraction of the diode ideality factor of a solar cell modeled by double junction behavior with considerable compliance. Various illumination intensities are also considered in order to specify the reliable limit of the method. The dependence of the ideality factor and the reverse saturation current with light intensity has also been investigated in order to provide insight into the alteration of electrical conduction at junction interface at room temperature.
ABSTRACT The dark alternating current (ac) parameters of BPW34 and BPW41 (Vishay-Telefunken) sili... more ABSTRACT The dark alternating current (ac) parameters of BPW34 and BPW41 (Vishay-Telefunken) silicon p-i-n photodiodes are measured and compared at different temperatures using the impedance spectroscopy technique. The impedance plots are nearly semicircular and typically distorted on the high frequency side. For BPW41, the distortion apparently arises from one of the two interfaces as expected for a typical p-i-n device. However, for BPW34, the presence of the distortion is attributed to the variation of photodiode capacitance and resistance with measurement frequency.
Impedance spectroscopy (IS) is a measurement technique which can be applied to any physical and e... more Impedance spectroscopy (IS) is a measurement technique which can be applied to any physical and electrochemical system modelled by an equivalent circuit consisting of resistor (R), capacitor (C) and inductor (L). In general, impedance of a physical system refers to all frequency dependent and independent resistivity effects opposed to the flow of current. In this work, theoretical real and complex impedance data are obtained by using Origin 7.0 programme for typical ac equivalent circuit models proposed for pn and pin junction type diodes in the frequency range in between 5 Hz -13 MHz. The dif-ferent steps of impedance data analysis are described with the help of Cole-Cole (Nyquist) and Bode graphical methods.
CdTe, CdS thin films and n-CdS/p-CdTe heterostructures have been prepared by conventional vacuum ... more CdTe, CdS thin films and n-CdS/p-CdTe heterostructures have been prepared by conventional vacuum evaporation technique. Some post deposition treatments to optimize the device efficiency have been analyzed and the effects of the individual process steps on the material and device properties were investigated. Annealing in air with and without CdCl2-treatment decreased the CdTe resistivity. The CdCl2-dip followed by annealing in air at 300°C for 5 min improved the grain size and polycrystalline nature of CdTe thin films. Solar efficiency improvements were achieved when heterojunctions were prepared on successively treated (i.e. etched, air annealed, CdCl2-processed) CdTe surfaces. Etching of the CdTe surface with potassium dichromate solution prior to metal contact deposition lead to the formation of low-resistance Au contacts and increase in open circuit voltage and fill factor values.
The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunc... more The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunction solar cells for temperatures below 300~K was investigated. The current-voltage properties of these solar cells is explained via tunnelling enhanced bulk and interface recombination models which give a quantitative description of the electronic loss mechanisms in the chalcopyrite-based heterojunction solar cells. The temperature dependence of the saturation current and the diode ideality factors of the as-grown and CdCl2 processed CdTe solar cells are shown to be well described by this model.
The paper presents a new analytical method for extracting the diode ideality factor of a p-n junc... more The paper presents a new analytical method for extracting the diode ideality factor of a p-n junction device using Lambert W-function model and the dark current-voltage data. The extracted values are found to be in good agreement with those calculated experimentally from dark current-voltage charac-teristics. Key Words: Ideality factor; Lambert W-function; Solar cell. 1.
The dark alternating current (ac) parameters of commercially available silicon p-i-n-photodiodes ... more The dark alternating current (ac) parameters of commercially available silicon p-i-n-photodiodes are measured and compared at room temperature both in forward and reverse bias using the impedance spectroscopy technique. The ac behavior of the photodiodes is found to be almost the same. For bias voltages in the range from −0.8 to 0.0 V, the typical photodiode behaves like a pure
The effects of post-deposition processes such as 0268-1242/12/5/014/img1 dip and/or annealing in ... more The effects of post-deposition processes such as 0268-1242/12/5/014/img1 dip and/or annealing in air on the material and device properties of vacuum-evaporated Au-CdTe/CdS-TO heterojunction solar cells have been investigated. The 0268-1242/12/5/014/img2 dip followed by air annealing at 0268-1242/12/5/014/img3 for 5 min improved the device efficiency significantly, resulting in decreased CdTe resistivity and enhanced grain size. The temperature-dependent current - voltage analysis indicated that above 280 K interface recombination dominates the current transport mechanism for the as-grown samples, while depletion region recombination starts to be dominant after annealing the samples with 0268-1242/12/5/014/img2. Below 280 K multistep tunnelling is identified to be the dominant transport mechanism. Frequency-dependent capacitance - voltage studies revealed that after annealing with 0268-1242/12/5/014/img2 the density of interface states decreases and the quality of the heterointerface improves. The capacitance of the CdS/CdTe heterojunctions has been analysed using a model based on the existence of a single dominant trap level, identified at 0.40 eV above the valence band with a concentration of 0268-1242/12/5/014/img6.
CdTe;CdS thin lms and n CdS=p CdTe heterostructures have been prepared by conventional vacuum eva... more CdTe;CdS thin lms and n CdS=p CdTe heterostructures have been prepared by conventional vacuum evaporation technique. Some post deposition treatments to optimize the device eciency have been analyzed and the eects of the individual process steps on the material and device properties were investigated. Annealing in air with and without CdCl2 -treatment decreased the CdTe resistivity. The CdCl2 -dip followed by annealing in air at 300C for 5 min improved the grain size and polycrystalline nature of CdTe thin lms. Solar eciency improvements were achieved when heterojunctions were prepared on successively treated (i.e. etched, air annealed, CdCl2 -processed) CdTe surfaces. Etching of the CdTe surface with potassium dichromate solution prior to metal contact deposition lead to the formation of low-resistance Au contacts and increase in open circuit voltage and ll factor values.
Measurements of the dark reverse current in a typical BPW34 silicon photodiode have been made in ... more Measurements of the dark reverse current in a typical BPW34 silicon photodiode have been made in the temperature range 100{300 K at various reverse bias voltages ranging from 0 to 60 V. Various transport models have been applied to analyze the temperature dependence of the reverse current-voltage data. We suggest that Bardeen’s model for a modied Schottky-like interfacial junction, that takes into account the eect of interfacial localized states, can be satisfactorily applied to describe the reverse current-voltage characteristics at bias voltages below 50 V.
This article presents a study on the energy distribution of defects in efficient thin film ZnO/Cd... more This article presents a study on the energy distribution of defects in efficient thin film ZnO/CdS/Cu(In,Ga)Se2 heterojunction solar cell by the use of admittance spectroscopy. The capacitance spectra of the device has been analyzed using a model based on the existence of a homogeneous distribution of bulk acceptors in the absorber Cu(In,Ga)Se2 layer. This model reveals an emission from a distribution of hole traps centered at an activation energy of about 300 meV with a defect density of 1.2 \times 1017 eV-1 cm-3. The band gap of the absorber layer is estimated to be about 1.46 eV which corresponds to a Ga content of about x \approx 0.7 with x the ratio Ga/(Ga+In).
The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunc... more The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunction solar cells for temperatures below 300~K was investigated. The current-voltage properties of these solar cells is explained via tunnelling enhanced bulk and interface recombination models which give a quantitative description of the electronic loss mechanisms in the chalcopyrite-based heterojunction solar cells. The temperature dependence of the saturation current and the diode ideality factors of the as-grown and CdCl2 processed CdTe solar cells are shown to be well described by this model.
The paper presents a new analytical method for extracting the diode ideality factor of a p-n junc... more The paper presents a new analytical method for extracting the diode ideality factor of a p-n junction device using Lambert W-function model and the dark current-voltage data. The extracted values are found to be in good agreement with those calculated experimentally from dark current-voltage characteristics.
Forward bias recombination (current transport) mechanisms have been evaluated for thin film solar... more Forward bias recombination (current transport) mechanisms have been evaluated for thin film solar cells and correlated to the in-gap trap levels present. Here CdTe/CdS devices were chosen as an archetypal example of a modern thin film solar cell, and a set of devices with a range of design variables was used in order to reveal the full range of behaviours that may operate to limit current transport. Experimental current–voltage–temperature datasets were compared to mathematical models of transport, and the in-gap traps were evaluated by thermal admittance spectroscopy. The current transport mechanisms operating are presented on a temperature–voltage diagram. Three regimes were identified: at 'intermediate' voltages, the behaviour was temperature dependent. From 300 K down to 240 K, thermally activated Shockley Read Hall recombination mediated by a 0.38 eV trap (V Cd) dominated the transport. Between 200 and 240 K the transport was thermally activated but below 200 K the mechanism became dominated by tunnel assisted interface recombination. At 'low' voltages (and for all devices at all voltages when measured at T < 200 K) band to band recombination is via multi-step tunnelling through in-gap states. At high voltage, the forward current is dominated by the well-known limiting effect of the back Schottky contact to the CdTe which is in reverse bias. The current transport behaviour is also correlated with the n-CdS thickness and CdCl2 processing conditions, both of which are critical to device performance.
A simple approach, which can estimate the barrier height of non-Ohmic back contacts for CdS/CdTe ... more A simple approach, which can estimate the barrier height of non-Ohmic back contacts for CdS/CdTe solar cell by using its temperature dependent forward biased current-voltage data, is explained. The method involves modelling the forward J–V characteristics using a double exponential expression for the main junction and by a reverse biased Schottky barrier for the back contact. Cells processed with both CdCl2 and MgCl2 are compared, with the current transport phenomena in both kinds of cells also being analysed. Performance loss due to limitation of the forward bias hole current, and its dependence on the post-deposition chloride processing, is discussed. The forward current transport is mainly dominated by recombination at CdS/CdTe interfacial region with pronounced tunnelling effects. Classical Schottky-type conduction, as described by the Richardson-Schottky formula, is a good fit to the reverse biased current-voltage behaviour of an Au/CdTe junction above ∼240 K. Below this temperature, the current limiting effect due to the increasing contribution from interfacial defect states can be satisfactorily explained by Bardeen’s model for a modified Schottky type barrier at back contact interface.
Abstract A simple approach, which can estimate the diode ideality factor of a high efficiency pn ... more Abstract A simple approach, which can estimate the diode ideality factor of a high efficiency pn junction solar cell under illumination by using its current–voltage data, is explained. We have proposed that an analytical method based on Lambert W-function is sufficient for the extraction of the diode ideality factor of a solar cell modeled by double junction behavior with considerable compliance. Various illumination intensities are also considered in order to specify the reliable limit of the method. The dependence of the ideality factor and the reverse saturation current with light intensity has also been investigated in order to provide insight into the alteration of electrical conduction at junction interface at room temperature.
ABSTRACT The dark alternating current (ac) parameters of BPW34 and BPW41 (Vishay-Telefunken) sili... more ABSTRACT The dark alternating current (ac) parameters of BPW34 and BPW41 (Vishay-Telefunken) silicon p-i-n photodiodes are measured and compared at different temperatures using the impedance spectroscopy technique. The impedance plots are nearly semicircular and typically distorted on the high frequency side. For BPW41, the distortion apparently arises from one of the two interfaces as expected for a typical p-i-n device. However, for BPW34, the presence of the distortion is attributed to the variation of photodiode capacitance and resistance with measurement frequency.
Impedance spectroscopy (IS) is a measurement technique which can be applied to any physical and e... more Impedance spectroscopy (IS) is a measurement technique which can be applied to any physical and electrochemical system modelled by an equivalent circuit consisting of resistor (R), capacitor (C) and inductor (L). In general, impedance of a physical system refers to all frequency dependent and independent resistivity effects opposed to the flow of current. In this work, theoretical real and complex impedance data are obtained by using Origin 7.0 programme for typical ac equivalent circuit models proposed for pn and pin junction type diodes in the frequency range in between 5 Hz -13 MHz. The dif-ferent steps of impedance data analysis are described with the help of Cole-Cole (Nyquist) and Bode graphical methods.
CdTe, CdS thin films and n-CdS/p-CdTe heterostructures have been prepared by conventional vacuum ... more CdTe, CdS thin films and n-CdS/p-CdTe heterostructures have been prepared by conventional vacuum evaporation technique. Some post deposition treatments to optimize the device efficiency have been analyzed and the effects of the individual process steps on the material and device properties were investigated. Annealing in air with and without CdCl2-treatment decreased the CdTe resistivity. The CdCl2-dip followed by annealing in air at 300°C for 5 min improved the grain size and polycrystalline nature of CdTe thin films. Solar efficiency improvements were achieved when heterojunctions were prepared on successively treated (i.e. etched, air annealed, CdCl2-processed) CdTe surfaces. Etching of the CdTe surface with potassium dichromate solution prior to metal contact deposition lead to the formation of low-resistance Au contacts and increase in open circuit voltage and fill factor values.
The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunc... more The dominant dark current transport mechanism in as-grown and CdCl2 processed CdS/CdTe heterojunction solar cells for temperatures below 300~K was investigated. The current-voltage properties of these solar cells is explained via tunnelling enhanced bulk and interface recombination models which give a quantitative description of the electronic loss mechanisms in the chalcopyrite-based heterojunction solar cells. The temperature dependence of the saturation current and the diode ideality factors of the as-grown and CdCl2 processed CdTe solar cells are shown to be well described by this model.
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