2017 IEEE Asia Pacific Microwave Conference (APMC), 2017
A Ka-band Doherty power amplifier (PA) is presented in this paper. The proposed Doherty PA is des... more A Ka-band Doherty power amplifier (PA) is presented in this paper. The proposed Doherty PA is designed using 0.15-μm GaAs enhancement-mode pHEMT process to achieve an output saturation power up to 25.1 dBm. The quarter-wave transmission lines and offset lines are implemented using inductance-capacitance lumped elements to reduce significantly the chip area. With a compact chip size of 1.5×1.5 mm2, the measured small signal gain, input and output return losses at 25.8 GHz are better than 7 dB, 15 dB, and 29 dB, respectively. The proposed Doherty PA achieves a peak power-added efficiency of 16.5% and a 6-dB back-off efficiency of 12.6%. This work has potential for the high-power high-efficiency communication system as compared to previously reported Doherty PAs.
A Ku-band power amplifier (PA) with T-model matching network is implemented using 0.25 µm GaN pHE... more A Ku-band power amplifier (PA) with T-model matching network is implemented using 0.25 µm GaN pHEMT process in this paper. To achieve broadband with high output power, the output matching of the PA is realized using the T-model matching network. Between 12 and 17 GHz, the small-signal gain and saturation output power (Psat) are higher than 12 dB and 29 dBm, resepectively. The measured maximum small-signal gain is 12 dB as the frequency is 16 GHz. When the supply voltage is 25 V, the proposed PA demonstrated a Psat of 27 dBm over the frequency, and a maximum power-added efficiency (PAE) of higher than 8% at 15 GHz.
In this paper, a negative body bias technique is employed to enhance the performance of a single-... more In this paper, a negative body bias technique is employed to enhance the performance of a single-port double-throw (SPDT) traveling-wave switch. The switch is fabricated using a commercial standard bulk 90 nm CMOS process. Between 30 and 92 GHz, the proposed circuit demonstrates an insertion loss of lower than 3.7 dB, an isolation of higher than 35 dB, an output 1-dB compression point (P1dB) of higher than 17 dBm, and an input third-order intercept point (IIP3) of higher than 28 dBm. The core area of the switch is 0.3 × 0.2 mm2. With the body bias, the insertion loss and the linearity of the switch are both improved since the parasitic capacitance of the NMOS device is further reduced. The design concept and theory calculation are also presented.
A low droop rate wide input bandwidth high dynamic range track-and-hold amplifier is proposed usi... more A low droop rate wide input bandwidth high dynamic range track-and-hold amplifier is proposed using 0.18 μm SiGe process in this paper. A master-slave track-and-hold topology is employed in the circuit design to further enhance the hold-mode isolation, and the measured droop rate is lower than $\mathbf{6\mu \mathbf{V}/\mathbf{ps}}$. A distributed amplifier is adopted for the input buffers and the clock buffers to widen the input bandwidth and sampling speed. Moreover, a differential feedthrough cancellation technique is employed in the track-and-hold stage to enhance isolation and linearity. With a total dc power consumption of 134 mW, the proposed THA features an input bandwidth of 10 GHz and an isolation of more than 50 dB. The measured spurious free dynamic range is 39.2 dB when the sampling rate is 7 GS/s.
In this paper, a F-band 90 nm CMOS frequency doubler using active CS-based Gm-boosted technique i... more In this paper, a F-band 90 nm CMOS frequency doubler using active CS-based Gm-boosted technique is proposed. When the Gm-boosted technique is applied to the frequency doubler design, the input driving power reduces due to the boosted input voltage swing. Therefore, the conversion gain can be improved. The proposed frequency doubler exhibits a conversion of -3.3 dB and a fractional bandwidth of 26.5%. At 60-GHz output frequency, the maximum output Psat is higher than 1 dBm with a maximum dc-to-RF conversion efficiency of 3.4% The output frequency is from 49 to 64 GHz with a fractional bandwidth of 26.5%.
In this letter, a 38–40 GHz high-speed IQ modulator using sub-harmonically injection-locked quadr... more In this letter, a 38–40 GHz high-speed IQ modulator using sub-harmonically injection-locked quadrature frequency-locked loop (FLL) is proposed. The IQ modulator consists of a quadrature FLL and four reflection-type modulators and it is implemented in a 90-nm complimentary metal–oxide–semiconductor (CMOS) process. With a sub-harmonic number of four, the proposed modulator features a locking range wider than 2 GHz, a maximum data rate of higher than 8 Gbps, and low error vector magnitudes (EVMs), among high-level QAM modulations. The modulation scheme can be up 128 QAM due to the low phase noise and low quadrature error of the FLL. The measured 128-QAM EVM is within 3%. With a data rate of 8 Gbps, the measured 16-QAM EVM is within 6%.
IEEE Transactions on Microwave Theory and Techniques
Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-lock... more Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness.
2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2016
Various kinds of broadband radio frequency integrated circuits for astronomical instrument were d... more Various kinds of broadband radio frequency integrated circuits for astronomical instrument were developed in Taiwan during past 18 years. In this paper the key technology and results, including the circuit design, testing, packaging and system integration are described.
2016 IEEE MTT-S International Microwave Symposium (IMS), 2016
An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SI... more An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90 nm CMOS process. To overcome the issue of narrow locking range, the control voltage of the SILVCO is adaptively adjusted using the FLL technique to refer to the sub-harmonic input frequency. This work demonstrates excellent robustness over temperature variation from 10°C to 70° C. Under the locking condition of the SILVCO with FLL, the measured minimum phase noise is -130.4 dBc/Hz at 1 MHz offset, the measured minimum jitter integrated from 50 kHz to 80 MHz is lower than 30.5 fs, and the output frequency is from 9.9 to 10.4 GHz. The circuit performance can be compared to the advanced CMOS low phase noise clock generators.
2015 IEEE MTT-S International Microwave Symposium, 2015
A 31.2% locking range K-band divide-by-6 frequency divider with regenerative injection-locked top... more A 31.2% locking range K-band divide-by-6 frequency divider with regenerative injection-locked topology is proposed using 90 nm CMOS process in this paper. The circuit is composed of a singly balanced mixer and a divide-by-5 injection-locked frequency divider (ILFD). The proposed frequency divider features high division, high speed, and wide locking range. The measured locking range is 7.1 GHz with an input power of -5 dBm. The measured output power and phase noise at 1 MHz offset are -5 dBm and -138.7 dBc/Hz, respectively This work has the widest locking range with good input sensitivity among the reported millimeter-wave ILFDs with division ratio higher than or equal to 5.
A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) us... more A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) using self-injection coupling (SIC) is proposed and demonstrated in 90 nm CMOS technology. By using SIC technique, this QVCO achieves low phase noise and good quadrature accuracy. Moreover, the amplitude/phase errors of the QVCO are fully characterized via a four-port vector network analyzer. The proposed 60-GHz QVCO exhibits a phase noise of -95 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.12 dB, and a phase errors of 1.2°. The dc power consumption is 13.3 mW with a supply voltage of 0.7 V. The chip size of the proposed QVCO is 0.75×0.6 mm2. This work has the lowest dc power consumption and the best figure-of-merits with high quadrature accuracy among the all reported millimeter-wave CMOS QVCOs.
This paper describes a K-band 2-element phase-array receiver in 90 nm CMOS process. The receiver ... more This paper describes a K-band 2-element phase-array receiver in 90 nm CMOS process. The receiver consists of two low noise amplifiers (LNAs), two vector modulators, and a down-converter mixer. The vector modulators are designed using a modified reflection-type in- and quadrature-phase modulator for amplitude and phase control. At 66 GHz, the measured small-signal gain of LNA is 24 dB with a noise figure of 6.9 dB. The measured small-signal gains of the LNA with the vector modulator for the four phase states are higher than 5 dB between 64 and 67 GHz. The measured conversion gain of mixer is 6.7 dB. The measured minimum phase and amplitude errors are 4.8 and 1 dB, respectively. The chip size is 1.45×0.95 mm2.
A 2×2 phased-array transmitter designed for V-band communications has been implemented by using C... more A 2×2 phased-array transmitter designed for V-band communications has been implemented by using CMOS 0.18 μm process. The circuit is based on a 30-GHz injection-locked oscillator (ILO) without using power amplifier. Combing a frequency doubler (FD) with the differential signal injection can generate a 60-GHz signal and perform a 360° phase shift with a harmonic suppression of 15 dBc. The
2014 IEEE MTT-S International Microwave Symposium (IMS2014), 2014
ABSTRACT A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The casc... more ABSTRACT A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage headroom and bandwidth. The input parasitic capacitance of the output buffer is designed as the hold-mode element to further reduce chip size. The dc supply voltage is 1.8 V with a total power consumption of 197 mW. When the input frequency is 2.42 GHz with an input voltage swing of 0.5 Vpp and the sampling rate is 12 GB/s, this work demonstrates a spur-free dynamic range of 48 dB, a total harmonic distortion of -45.8 dB, and an input bandwidth of 3 GHz.
2017 IEEE Asia Pacific Microwave Conference (APMC), 2017
A Ka-band Doherty power amplifier (PA) is presented in this paper. The proposed Doherty PA is des... more A Ka-band Doherty power amplifier (PA) is presented in this paper. The proposed Doherty PA is designed using 0.15-μm GaAs enhancement-mode pHEMT process to achieve an output saturation power up to 25.1 dBm. The quarter-wave transmission lines and offset lines are implemented using inductance-capacitance lumped elements to reduce significantly the chip area. With a compact chip size of 1.5×1.5 mm2, the measured small signal gain, input and output return losses at 25.8 GHz are better than 7 dB, 15 dB, and 29 dB, respectively. The proposed Doherty PA achieves a peak power-added efficiency of 16.5% and a 6-dB back-off efficiency of 12.6%. This work has potential for the high-power high-efficiency communication system as compared to previously reported Doherty PAs.
A Ku-band power amplifier (PA) with T-model matching network is implemented using 0.25 µm GaN pHE... more A Ku-band power amplifier (PA) with T-model matching network is implemented using 0.25 µm GaN pHEMT process in this paper. To achieve broadband with high output power, the output matching of the PA is realized using the T-model matching network. Between 12 and 17 GHz, the small-signal gain and saturation output power (Psat) are higher than 12 dB and 29 dBm, resepectively. The measured maximum small-signal gain is 12 dB as the frequency is 16 GHz. When the supply voltage is 25 V, the proposed PA demonstrated a Psat of 27 dBm over the frequency, and a maximum power-added efficiency (PAE) of higher than 8% at 15 GHz.
In this paper, a negative body bias technique is employed to enhance the performance of a single-... more In this paper, a negative body bias technique is employed to enhance the performance of a single-port double-throw (SPDT) traveling-wave switch. The switch is fabricated using a commercial standard bulk 90 nm CMOS process. Between 30 and 92 GHz, the proposed circuit demonstrates an insertion loss of lower than 3.7 dB, an isolation of higher than 35 dB, an output 1-dB compression point (P1dB) of higher than 17 dBm, and an input third-order intercept point (IIP3) of higher than 28 dBm. The core area of the switch is 0.3 × 0.2 mm2. With the body bias, the insertion loss and the linearity of the switch are both improved since the parasitic capacitance of the NMOS device is further reduced. The design concept and theory calculation are also presented.
A low droop rate wide input bandwidth high dynamic range track-and-hold amplifier is proposed usi... more A low droop rate wide input bandwidth high dynamic range track-and-hold amplifier is proposed using 0.18 μm SiGe process in this paper. A master-slave track-and-hold topology is employed in the circuit design to further enhance the hold-mode isolation, and the measured droop rate is lower than $\mathbf{6\mu \mathbf{V}/\mathbf{ps}}$. A distributed amplifier is adopted for the input buffers and the clock buffers to widen the input bandwidth and sampling speed. Moreover, a differential feedthrough cancellation technique is employed in the track-and-hold stage to enhance isolation and linearity. With a total dc power consumption of 134 mW, the proposed THA features an input bandwidth of 10 GHz and an isolation of more than 50 dB. The measured spurious free dynamic range is 39.2 dB when the sampling rate is 7 GS/s.
In this paper, a F-band 90 nm CMOS frequency doubler using active CS-based Gm-boosted technique i... more In this paper, a F-band 90 nm CMOS frequency doubler using active CS-based Gm-boosted technique is proposed. When the Gm-boosted technique is applied to the frequency doubler design, the input driving power reduces due to the boosted input voltage swing. Therefore, the conversion gain can be improved. The proposed frequency doubler exhibits a conversion of -3.3 dB and a fractional bandwidth of 26.5%. At 60-GHz output frequency, the maximum output Psat is higher than 1 dBm with a maximum dc-to-RF conversion efficiency of 3.4% The output frequency is from 49 to 64 GHz with a fractional bandwidth of 26.5%.
In this letter, a 38–40 GHz high-speed IQ modulator using sub-harmonically injection-locked quadr... more In this letter, a 38–40 GHz high-speed IQ modulator using sub-harmonically injection-locked quadrature frequency-locked loop (FLL) is proposed. The IQ modulator consists of a quadrature FLL and four reflection-type modulators and it is implemented in a 90-nm complimentary metal–oxide–semiconductor (CMOS) process. With a sub-harmonic number of four, the proposed modulator features a locking range wider than 2 GHz, a maximum data rate of higher than 8 Gbps, and low error vector magnitudes (EVMs), among high-level QAM modulations. The modulation scheme can be up 128 QAM due to the low phase noise and low quadrature error of the FLL. The measured 128-QAM EVM is within 3%. With a data rate of 8 Gbps, the measured 16-QAM EVM is within 6%.
IEEE Transactions on Microwave Theory and Techniques
Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-lock... more Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness.
2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2016
Various kinds of broadband radio frequency integrated circuits for astronomical instrument were d... more Various kinds of broadband radio frequency integrated circuits for astronomical instrument were developed in Taiwan during past 18 years. In this paper the key technology and results, including the circuit design, testing, packaging and system integration are described.
2016 IEEE MTT-S International Microwave Symposium (IMS), 2016
An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SI... more An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90 nm CMOS process. To overcome the issue of narrow locking range, the control voltage of the SILVCO is adaptively adjusted using the FLL technique to refer to the sub-harmonic input frequency. This work demonstrates excellent robustness over temperature variation from 10°C to 70° C. Under the locking condition of the SILVCO with FLL, the measured minimum phase noise is -130.4 dBc/Hz at 1 MHz offset, the measured minimum jitter integrated from 50 kHz to 80 MHz is lower than 30.5 fs, and the output frequency is from 9.9 to 10.4 GHz. The circuit performance can be compared to the advanced CMOS low phase noise clock generators.
2015 IEEE MTT-S International Microwave Symposium, 2015
A 31.2% locking range K-band divide-by-6 frequency divider with regenerative injection-locked top... more A 31.2% locking range K-band divide-by-6 frequency divider with regenerative injection-locked topology is proposed using 90 nm CMOS process in this paper. The circuit is composed of a singly balanced mixer and a divide-by-5 injection-locked frequency divider (ILFD). The proposed frequency divider features high division, high speed, and wide locking range. The measured locking range is 7.1 GHz with an input power of -5 dBm. The measured output power and phase noise at 1 MHz offset are -5 dBm and -138.7 dBc/Hz, respectively This work has the widest locking range with good input sensitivity among the reported millimeter-wave ILFDs with division ratio higher than or equal to 5.
A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) us... more A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) using self-injection coupling (SIC) is proposed and demonstrated in 90 nm CMOS technology. By using SIC technique, this QVCO achieves low phase noise and good quadrature accuracy. Moreover, the amplitude/phase errors of the QVCO are fully characterized via a four-port vector network analyzer. The proposed 60-GHz QVCO exhibits a phase noise of -95 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.12 dB, and a phase errors of 1.2°. The dc power consumption is 13.3 mW with a supply voltage of 0.7 V. The chip size of the proposed QVCO is 0.75×0.6 mm2. This work has the lowest dc power consumption and the best figure-of-merits with high quadrature accuracy among the all reported millimeter-wave CMOS QVCOs.
This paper describes a K-band 2-element phase-array receiver in 90 nm CMOS process. The receiver ... more This paper describes a K-band 2-element phase-array receiver in 90 nm CMOS process. The receiver consists of two low noise amplifiers (LNAs), two vector modulators, and a down-converter mixer. The vector modulators are designed using a modified reflection-type in- and quadrature-phase modulator for amplitude and phase control. At 66 GHz, the measured small-signal gain of LNA is 24 dB with a noise figure of 6.9 dB. The measured small-signal gains of the LNA with the vector modulator for the four phase states are higher than 5 dB between 64 and 67 GHz. The measured conversion gain of mixer is 6.7 dB. The measured minimum phase and amplitude errors are 4.8 and 1 dB, respectively. The chip size is 1.45×0.95 mm2.
A 2×2 phased-array transmitter designed for V-band communications has been implemented by using C... more A 2×2 phased-array transmitter designed for V-band communications has been implemented by using CMOS 0.18 μm process. The circuit is based on a 30-GHz injection-locked oscillator (ILO) without using power amplifier. Combing a frequency doubler (FD) with the differential signal injection can generate a 60-GHz signal and perform a 360° phase shift with a harmonic suppression of 15 dBc. The
2014 IEEE MTT-S International Microwave Symposium (IMS2014), 2014
ABSTRACT A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The casc... more ABSTRACT A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage headroom and bandwidth. The input parasitic capacitance of the output buffer is designed as the hold-mode element to further reduce chip size. The dc supply voltage is 1.8 V with a total power consumption of 197 mW. When the input frequency is 2.42 GHz with an input voltage swing of 0.5 Vpp and the sampling rate is 12 GB/s, this work demonstrates a spur-free dynamic range of 48 dB, a total harmonic distortion of -45.8 dB, and an input bandwidth of 3 GHz.
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Papers by Hong-Yeh Chang