Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 In... more ... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 IntroductionModem IC manufacturing is characterized by steeply ris-ing costs: fabrication line costs have doubled every generation, to $1-2 billion today [1,2]. An important component of cost is ...
This work describes DFT/DFD/DFM strategies implemented on a 40 Gbps framer chip. The device is a ... more This work describes DFT/DFD/DFM strategies implemented on a 40 Gbps framer chip. The device is a 1500 pin, over 10M gate SoC with multiple PLLs/DLLs and 2.5 GHz IOs. Some novel techniques were required to ensure quality and manufacturability. It also describes the various area and design complexity trade-offs that went into the design process.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Abstract Success of the fabless model has increased competition and has put pressure on design ho... more Abstract Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and ...
This paper proposes a vision for a new research domain emerging on the interface between design a... more This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important task is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well. Introduction The design-manufacturing interface can be seen as having evolved through three ...
This paper describes a new methodology for rapid failure analysis. The methodology is based on th... more This paper describes a new methodology for rapid failure analysis. The methodology is based on the contamination- defect-fault (CDF) simulator CODEF, which is able to map the effects of contamination deposited on an IC cell during any stage of the manufacturing process, onto circuit-level faults. The utilization of CODEF's capabilities-in both single contamination mode and Monte Carlo mode-in speeding up failure analysis is illustrated in the paper with examples.
In conjunction with the new contamination model and in accordance with the simulation requirement... more In conjunction with the new contamination model and in accordance with the simulation requirements (both described in Chapter 3), a contamination-defect-fault mapping tool CODEF (Contamination-Defect-Fault) [1], [2], [3] has been developed. A block diagram of the simulator is shown in Figure 1. CODEF accepts as inputs (a) layout description of the IC cell under analysis in CIF format [4], (b) description of the fabrication process (process recipe) in the PREDITOR format [5], [6], and (c) statistics of contamination parameters for each processing step of interest.
As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faul... more As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faults starting from the actual failure mechanism, rather than from the spot defect level. It was also observed in the model validation experiment [1], [2], [3] and in the experiment described in [4] that most failures in ICs were caused by contamination which deposited on the IC during some processing step. To increase the fidelity of modeling, therefore, it is essential to begin all fault and yield model studies/simulations at the contamination level.
Discusses the use of special test structures and algorithms needed to extract the defect characte... more Discusses the use of special test structures and algorithms needed to extract the defect characteristics for accurate yield estimation. By using the double bridge test structure, which can be applied to obtain defect size distributions in the metal layer, the basic elements of the defect extraction algorithms are demonstrated. Data from a fabrication experiment is used to illustrate the algorithms
Over the years there has been a large increase in the functionality available on a single integra... more Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
ABSTRACT In modern VLSI processes, increasing process complexity has resulted in an exponential r... more ABSTRACT In modern VLSI processes, increasing process complexity has resulted in an exponential rise in the costs of thorough failure analysis. In this paper, we present a defect simulation-based failure analysis methodology, which can be used to significantly reduce both costs and turn-around time for failure analyses. The methodology is based on the ability to generate a defect dictionary, which can relate defect characteristics to some easily measurable symptoms of defect occurrence.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 In... more ... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 IntroductionModem IC manufacturing is characterized by steeply ris-ing costs: fabrication line costs have doubled every generation, to $1-2 billion today [1,2]. An important component of cost is ...
This work describes DFT/DFD/DFM strategies implemented on a 40 Gbps framer chip. The device is a ... more This work describes DFT/DFD/DFM strategies implemented on a 40 Gbps framer chip. The device is a 1500 pin, over 10M gate SoC with multiple PLLs/DLLs and 2.5 GHz IOs. Some novel techniques were required to ensure quality and manufacturability. It also describes the various area and design complexity trade-offs that went into the design process.
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Abstract Success of the fabless model has increased competition and has put pressure on design ho... more Abstract Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and ...
This paper proposes a vision for a new research domain emerging on the interface between design a... more This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important task is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well. Introduction The design-manufacturing interface can be seen as having evolved through three ...
This paper describes a new methodology for rapid failure analysis. The methodology is based on th... more This paper describes a new methodology for rapid failure analysis. The methodology is based on the contamination- defect-fault (CDF) simulator CODEF, which is able to map the effects of contamination deposited on an IC cell during any stage of the manufacturing process, onto circuit-level faults. The utilization of CODEF's capabilities-in both single contamination mode and Monte Carlo mode-in speeding up failure analysis is illustrated in the paper with examples.
In conjunction with the new contamination model and in accordance with the simulation requirement... more In conjunction with the new contamination model and in accordance with the simulation requirements (both described in Chapter 3), a contamination-defect-fault mapping tool CODEF (Contamination-Defect-Fault) [1], [2], [3] has been developed. A block diagram of the simulator is shown in Figure 1. CODEF accepts as inputs (a) layout description of the IC cell under analysis in CIF format [4], (b) description of the fabrication process (process recipe) in the PREDITOR format [5], [6], and (c) statistics of contamination parameters for each processing step of interest.
As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faul... more As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faults starting from the actual failure mechanism, rather than from the spot defect level. It was also observed in the model validation experiment [1], [2], [3] and in the experiment described in [4] that most failures in ICs were caused by contamination which deposited on the IC during some processing step. To increase the fidelity of modeling, therefore, it is essential to begin all fault and yield model studies/simulations at the contamination level.
Discusses the use of special test structures and algorithms needed to extract the defect characte... more Discusses the use of special test structures and algorithms needed to extract the defect characteristics for accurate yield estimation. By using the double bridge test structure, which can be applied to obtain defect size distributions in the metal layer, the basic elements of the defect extraction algorithms are demonstrated. Data from a fabrication experiment is used to illustrate the algorithms
Over the years there has been a large increase in the functionality available on a single integra... more Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
ABSTRACT In modern VLSI processes, increasing process complexity has resulted in an exponential r... more ABSTRACT In modern VLSI processes, increasing process complexity has resulted in an exponential rise in the costs of thorough failure analysis. In this paper, we present a defect simulation-based failure analysis methodology, which can be used to significantly reduce both costs and turn-around time for failure analyses. The methodology is based on the ability to generate a defect dictionary, which can relate defect characteristics to some easily measurable symptoms of defect occurrence.
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