Temperature effect on the reliability of ZrO2 gate dielectric has been presented. High effective ... more Temperature effect on the reliability of ZrO2 gate dielectric has been presented. High effective voltage-ramp breakdown field was observed. The activation energy of temperature accelerated voltage-ramp breakdown calculated from Arrhenius plot indicates that the breakdown of ZrO2 is less sensitive to temperature than a thermal oxide of similar electrical thickness. ZrO2 films exhibit excellent TDDB characteristics with low charge trapping and no stress induced leakage current. The field and temperature acceleration for TDDB for the 15.8 Å capacitance equivalent oxide thickness (CET) ZrO2 shows that the activation energy for TDDB falls into the range reported for oxide from 39 Å to 150 Å. It was found that the extrapolated 10-year lifetime operating voltage can be as high as -1.9 V, even at 150°C based on the “log(tBD) vs E” extrapolation model for a film with a CET of 15.8 Å
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si have been i... more MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si have been investigated. Thin equivalent oxide thickness (EOT), low leakage, negligible frequency dispersion, interface density less than 1011 cm-2 eV-1, small hysteresis, excellent reliability characteristics have been demonstrated. The ZrO2 film has been shown to be amorphous. A thin interfacial Zr-silicate layer (k>8) exists and is beneficial in
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
Physical, electrical and reliability characteristics of ultra thin Hf02 as an alternative gate di... more Physical, electrical and reliability characteristics of ultra thin Hf02 as an alternative gate dielectric were studied for the first time. Crucial process parameters of oxygen modulated dc magnetron sputtering were optimized to achieve an equivalent oxide thickness(E0T) of 1 1.5A ...
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000
In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO2 an... more In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO2 and Zr-silicate gate dielectrics. These high-k films exhibit low leakage, low subthreshold swing (S), and good on-off characteristics. Good effective electron and hole mobilities were obtained. It was found that for Zr-silicate, a mobility closer to thermal SiO2 was demonstrated due to the better
2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03), 2003
ABSTRACT This paper describes how SOI film thickness affects performance and power consumption of... more ABSTRACT This paper describes how SOI film thickness affects performance and power consumption of a Partially-Depleted (PD) SOI microprocessor. System level speed/power performance will be compared directly between chips fabricated with different SOI film thickness. The performance improvement is also supported by device level and macro circuit level comparison. Yield issues associated with thinner SOI will also be addressed.
Hysteresis effect of barium strontium titanate (BST) thin films for gate dielectric application h... more Hysteresis effect of barium strontium titanate (BST) thin films for gate dielectric application has been studied. It is found that the “counterclockwise” hysteresis has strong sweep voltage and operating temperature dependence. It can be reduced or eliminated by proper thermal annealing or by using a barrier layer. A charge trapping and detrapping mechanism has been proposed.
ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate diele... more ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the inte...
ABSTRACT In this paper, we present a high performance planar 20nm CMOS bulk technology for low po... more ABSTRACT In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.
Temperature effect on the reliability of ZrO2 gate dielectric has been presented. High effective ... more Temperature effect on the reliability of ZrO2 gate dielectric has been presented. High effective voltage-ramp breakdown field was observed. The activation energy of temperature accelerated voltage-ramp breakdown calculated from Arrhenius plot indicates that the breakdown of ZrO2 is less sensitive to temperature than a thermal oxide of similar electrical thickness. ZrO2 films exhibit excellent TDDB characteristics with low charge trapping and no stress induced leakage current. The field and temperature acceleration for TDDB for the 15.8 Å capacitance equivalent oxide thickness (CET) ZrO2 shows that the activation energy for TDDB falls into the range reported for oxide from 39 Å to 150 Å. It was found that the extrapolated 10-year lifetime operating voltage can be as high as -1.9 V, even at 150°C based on the “log(tBD) vs E” extrapolation model for a film with a CET of 15.8 Å
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si have been i... more MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si have been investigated. Thin equivalent oxide thickness (EOT), low leakage, negligible frequency dispersion, interface density less than 1011 cm-2 eV-1, small hysteresis, excellent reliability characteristics have been demonstrated. The ZrO2 film has been shown to be amorphous. A thin interfacial Zr-silicate layer (k>8) exists and is beneficial in
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
Physical, electrical and reliability characteristics of ultra thin Hf02 as an alternative gate di... more Physical, electrical and reliability characteristics of ultra thin Hf02 as an alternative gate dielectric were studied for the first time. Crucial process parameters of oxygen modulated dc magnetron sputtering were optimized to achieve an equivalent oxide thickness(E0T) of 1 1.5A ...
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000
In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO2 an... more In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO2 and Zr-silicate gate dielectrics. These high-k films exhibit low leakage, low subthreshold swing (S), and good on-off characteristics. Good effective electron and hole mobilities were obtained. It was found that for Zr-silicate, a mobility closer to thermal SiO2 was demonstrated due to the better
2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03), 2003
ABSTRACT This paper describes how SOI film thickness affects performance and power consumption of... more ABSTRACT This paper describes how SOI film thickness affects performance and power consumption of a Partially-Depleted (PD) SOI microprocessor. System level speed/power performance will be compared directly between chips fabricated with different SOI film thickness. The performance improvement is also supported by device level and macro circuit level comparison. Yield issues associated with thinner SOI will also be addressed.
Hysteresis effect of barium strontium titanate (BST) thin films for gate dielectric application h... more Hysteresis effect of barium strontium titanate (BST) thin films for gate dielectric application has been studied. It is found that the “counterclockwise” hysteresis has strong sweep voltage and operating temperature dependence. It can be reduced or eliminated by proper thermal annealing or by using a barrier layer. A charge trapping and detrapping mechanism has been proposed.
ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate diele... more ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the inte...
ABSTRACT In this paper, we present a high performance planar 20nm CMOS bulk technology for low po... more ABSTRACT In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.
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Papers by Laegu Kang