Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-ba... more Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-based sytems. This is true due to the cubic relation between the dynamic power consumption and the supply voltage. The main roadblock during aggressive voltage scaling is that the reliability of the circuits and especially of memory structures (SRAM cells) is exponentially decreased. The usage of well-known error correction codes (ECC) can only remedy a part of the problem. ECC have been proposed to protect the lower level caches (e.g., L2 or L3), but ECC cannot be employed in single-cycle first level caches due to their performance sensitivity to the additional latency of ECC. In this work, we propose a methodology to solve this problem by exploring the use of criticality metrics in aggressive superscalar processors. Instead of disabling the faulty frames of a faulty cache (as proposed in related work), we keep these frame " alive " (data are still placed and accessed in these f...
A new statistical test data compression method that is suitable for IP cores of an unknown struct... more A new statistical test data compression method that is suitable for IP cores of an unknown structure with multiple scan chains is proposed in this paper. Huffman, which is a well-known fixed-to-variable code, is used in this paper as a variable-to-variable code. The precomputed test set of a core is partitioned into variable-length blocks, which are, then, compressed by an efficient Huffman-based encoding procedure with a limited number of codewords. To increase the compression ratio, the same codeword can be reused for encoding compatible blocks of different sizes. Further compression improvements can be achieved by using two very simple test set transformations. A simple and low-overhead decompression architecture is also proposed.
This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code chec... more This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code checkers taking into account a realistic fault model including stuck-at, transistor stuck-on, transistor stuck-open, resistive bridging faults and breaks. The proposed design method is the first method in the open literature that takes into account a realistic fault model and can be applied for most practical values of m and n. Apart from the above the proposed checkers are very compact and very fast. The single output checkers are near optimal with respect to the number of transistors required for their implementation. Another benefit of the proposed TSC checkers is that all faults are tested by a very small set of single pattern tests, thus the probability of achieving the TSC goal is greater than in checkers requiring two-pattern tests. The single output TSC checkers proposed in this paper are the first known single output TSC checkers for m-out-of-n codes.
11. PRELIMINARIES sub-circuit N* Abstract-In this paper a new method to design totally self-check... more 11. PRELIMINARIES sub-circuit N* Abstract-In this paper a new method to design totally self-checking (TSC) checkers for a class of Borden codes is given and their applicabil- ity is discussed. The TSC checkers designed in this paper are impres- sively more efficient, with respect to implementation cost and speed, than the corresponding checkers hitherto proposed in the literature.
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003, 2000
In this paper we at first reveal the cyclic nature of idempotency in the case of modulo 2n − 1 ad... more In this paper we at first reveal the cyclic nature of idempotency in the case of modulo 2n − 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n − 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2000
ABSTRACT In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adder... more ABSTRACT In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adders, for every n, is introduced. The resulting modulo 2n - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area × time complexity reduction of up to 46% when compared to previously reported designs.
The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix add... more The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. ... The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. ...
Zero treatment in diminished-one modulo 2 + 1 addition has traditionally been performed separatel... more Zero treatment in diminished-one modulo 2 + 1 addition has traditionally been performed separately, leading to slow and area-consuming implementations. To overcome this, on the basis of an enhanced number representation used previously, we introduce novel carry look ahead and parallel-prefix architectures for diminished-one modulo 2 + 1 adders that can also handle operands equal to 0. Translators for the
Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-ba... more Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-based sytems. This is true due to the cubic relation between the dynamic power consumption and the supply voltage. The main roadblock during aggressive voltage scaling is that the reliability of the circuits and especially of memory structures (SRAM cells) is exponentially decreased. The usage of well-known error correction codes (ECC) can only remedy a part of the problem. ECC have been proposed to protect the lower level caches (e.g., L2 or L3), but ECC cannot be employed in single-cycle first level caches due to their performance sensitivity to the additional latency of ECC. In this work, we propose a methodology to solve this problem by exploring the use of criticality metrics in aggressive superscalar processors. Instead of disabling the faulty frames of a faulty cache (as proposed in related work), we keep these frame " alive " (data are still placed and accessed in these f...
A new statistical test data compression method that is suitable for IP cores of an unknown struct... more A new statistical test data compression method that is suitable for IP cores of an unknown structure with multiple scan chains is proposed in this paper. Huffman, which is a well-known fixed-to-variable code, is used in this paper as a variable-to-variable code. The precomputed test set of a core is partitioned into variable-length blocks, which are, then, compressed by an efficient Huffman-based encoding procedure with a limited number of codewords. To increase the compression ratio, the same codeword can be reused for encoding compatible blocks of different sizes. Further compression improvements can be achieved by using two very simple test set transformations. A simple and low-overhead decompression architecture is also proposed.
This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code chec... more This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code checkers taking into account a realistic fault model including stuck-at, transistor stuck-on, transistor stuck-open, resistive bridging faults and breaks. The proposed design method is the first method in the open literature that takes into account a realistic fault model and can be applied for most practical values of m and n. Apart from the above the proposed checkers are very compact and very fast. The single output checkers are near optimal with respect to the number of transistors required for their implementation. Another benefit of the proposed TSC checkers is that all faults are tested by a very small set of single pattern tests, thus the probability of achieving the TSC goal is greater than in checkers requiring two-pattern tests. The single output TSC checkers proposed in this paper are the first known single output TSC checkers for m-out-of-n codes.
11. PRELIMINARIES sub-circuit N* Abstract-In this paper a new method to design totally self-check... more 11. PRELIMINARIES sub-circuit N* Abstract-In this paper a new method to design totally self-checking (TSC) checkers for a class of Borden codes is given and their applicabil- ity is discussed. The TSC checkers designed in this paper are impres- sively more efficient, with respect to implementation cost and speed, than the corresponding checkers hitherto proposed in the literature.
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003, 2000
In this paper we at first reveal the cyclic nature of idempotency in the case of modulo 2n − 1 ad... more In this paper we at first reveal the cyclic nature of idempotency in the case of modulo 2n − 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n − 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2000
ABSTRACT In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adder... more ABSTRACT In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adders, for every n, is introduced. The resulting modulo 2n - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area × time complexity reduction of up to 46% when compared to previously reported designs.
The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix add... more The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. ... The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. ...
Zero treatment in diminished-one modulo 2 + 1 addition has traditionally been performed separatel... more Zero treatment in diminished-one modulo 2 + 1 addition has traditionally been performed separately, leading to slow and area-consuming implementations. To overcome this, on the basis of an enhanced number representation used previously, we introduce novel carry look ahead and parallel-prefix architectures for diminished-one modulo 2 + 1 adders that can also handle operands equal to 0. Translators for the
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Papers by Dimitris Nikolos