Integrating compound semiconductors with silicon CMOS has been critical for the success of the co... more Integrating compound semiconductors with silicon CMOS has been critical for the success of the commercial wireless communications industry, especially at macroscopic integration nodes (board-level, MCM, etc). With continued scaling of system bandwidth and power requirements, RF and mixed-signal microsystems can benefit from 2.5D and 3D heterogeneous integration techniques with finer size and pitch interconnects. Chemical-mechanical-polishing (CMP) becomes a critical tool for these interconnects. We outline our findings during development of CMP processes on compound semiconductor substrates (InP and SiC) substrates, and present measurement results from integrated parts. Developments include: CMP polishing of SiO and metals (Cu and W); and controlled wafer thinning of bonded InP and Si wafers to <10 m final thickness.
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2020
Low Gain Avalanche Detectors (LGADs) have recently been studied for applications in high energy p... more Low Gain Avalanche Detectors (LGADs) have recently been studied for applications in high energy physics. They provide the advantages of built-in gain and fast read-out. However, radiation hardness remains a problem, reduced effective boron doping concentration (acceptor removal) after hadron irradiation that dramatically reduces LGAD gain. We propose a new LGAD process flow that allows for creation of a very steep boron profile in the multiplication region, reducing the fractional acceptor removal and resulting performance degradation. The new LGAD process flow requires a low temperature silicon-silicon wafer bonding process, which is currently under development. TCAD process simulations are used to demonstrate feasibility of the new structure, and TCAD device simulations are used to characterize LGAD performance before and after irradiation.
available system bandwidth. This TDC has a two buffer input quew and a four buffa ouqntt qucuh Af... more available system bandwidth. This TDC has a two buffer input quew and a four buffa ouqntt qucuh Aftw an event is A prototype 64 channel Fastbus TDC built at Fermilab is acqubcd. input buffers can be swapped in about 50 nsec. Two described The module features a full custom CMOS fom hit capability is implemented with 40 tuec double pulse chatmel gad integnuu chip. one level of analog buffering at t-esoIutimt. Only tints fmn hit channels is di&izcd and written the inputs is impkmented cm chip. A four event dce.p output info rhe output queue. Tlti.3 queue allows events to be acquired queue at the bus interface allows * bigb event rate with low and read cut simultaneously. With these hvo queues. both the dead time. Each channel can record up to hvo hits per event cm card digitizing system and tie aatc readout system can be With an occupation rate of 10%. the module can opcmtc at rmtuing at nearly maximum capaeity with vuy low deadtime. 40,ooO events per seccd with dead time on the order o...
CROSS CONNECT SWITCH A reconfigurable memory having M bit lines and a plurality of row lines, whe... more CROSS CONNECT SWITCH A reconfigurable memory having M bit lines and a plurality of row lines, where MZ1. The memory includes an array of memory Storage cells, each memory Storage cell Storing a data value. The data value is read from or into the Storage cells by coupling that data value to one of the bit lines in response to a row control Signal on one of the row lines. A row Select circuit generates the row control Signal on one of the row lines in response to a row address being coupled to the row Select circuit. The row Select circuit includes a memory for Storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of Sense amplifiers, one Such Sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory Storage cells both at power up and run time to detect def...
Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D ... more Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D DRAM will be presented along with the plans (and possibly some results) of further integration with other 3D host logic devices. Additionally, results from several other recent 3D integrations will be reviewed.
Tezzaron has worked for several years in the area of 3D integrated circuit development. During 20... more Tezzaron has worked for several years in the area of 3D integrated circuit development. During 2010, 3 different multiproject wafer runs targeting 2 to 5 layer 3DICs for several different customers were started. Tezzaron's perspective on the results of those runs, issues, and futures will be discussed.
This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology includin... more This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to wafer integration of InP and GaAs with CMOS devices and new work in bonded die to wafer assembly with sub 25um pitch. A manufacturing perspective of the evolving customer requirements and the unique challenges in testing these highly complex devices will be discussed.
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12, 2012
Summary form only given. Moore's law predicted the sustained scaling the semiconductor indust... more Summary form only given. Moore's law predicted the sustained scaling the semiconductor industry has enjoyed for decades, but in the coming decade the limits of physics will force the pace of geometric scaling to slow and perhaps all but stop. In the face of this issue, the electronics industry needs alternatives that can give end consumers the continual increase in function and reduction in cost that they have come to expect. 3D integrated circuits have emerged as the near term solution to mitigate the roll-off of geometric semiconductor scaling. The power of 3D circuit integration comes from its ability to reduce wire length. The ramifications of this are more numerous and powerful than one might initially realize. The shortened wires improve speed and reduce power, but they also allow new combinations of technologies optimized for the performance of specific circuitry. 3D wiring changes alone might provide a 5-30% device improvement, but combining disparate circuit types and using 3D optimized architectures could enable 100-500% improvements. This paper discusses the benefits of 3D and the methods of producing various types of 3D and examines various examples ranging from imagers to exascale computing memories. It also presents an overview of the new requirements that 3D EDA tools must address to effectively handle 3D integration and describes some of the tools that are already available.
Proceedings of the 2011 international symposium on Physical design - ISPD '11, 2011
In this paper, we describe the developments over the past several years in field of 3D integrated... more In this paper, we describe the developments over the past several years in field of 3D integrated circuits. 3D integration offers far greater improvements than traditional semiconductor scaling can provide today. Considered part of the "More Than Moore" category of semiconductor technology, in addition to increasing circuit and system density, 3D integrated circuits can blend a wide range of materials and technologies into a signal polylithic device acting as if these disparate items were truly fabricated together on a single wafer. 3D offers improvement in power, speed, density, cost and reliability, but to access these, new design techniques and system architectures must be used. The paper will review various 3D integration techniques, tool requirements, application of advanced test methodologies, and results.
This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like mater... more This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like materials or components – but also provides information about homogeneous 3D assemblies in combination with other 2D or 3D devices. One example of homogeneous integration is the stacking of memory layers to create a 3D memory device. In such a device, the component layers are usually made of the same material and are often virtually identical in design. This chapter uses 3D DRAM as a reference application.
Integrating compound semiconductors with silicon CMOS has been critical for the success of the co... more Integrating compound semiconductors with silicon CMOS has been critical for the success of the commercial wireless communications industry, especially at macroscopic integration nodes (board-level, MCM, etc). With continued scaling of system bandwidth and power requirements, RF and mixed-signal microsystems can benefit from 2.5D and 3D heterogeneous integration techniques with finer size and pitch interconnects. Chemical-mechanical-polishing (CMP) becomes a critical tool for these interconnects. We outline our findings during development of CMP processes on compound semiconductor substrates (InP and SiC) substrates, and present measurement results from integrated parts. Developments include: CMP polishing of SiO and metals (Cu and W); and controlled wafer thinning of bonded InP and Si wafers to <10 m final thickness.
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2020
Low Gain Avalanche Detectors (LGADs) have recently been studied for applications in high energy p... more Low Gain Avalanche Detectors (LGADs) have recently been studied for applications in high energy physics. They provide the advantages of built-in gain and fast read-out. However, radiation hardness remains a problem, reduced effective boron doping concentration (acceptor removal) after hadron irradiation that dramatically reduces LGAD gain. We propose a new LGAD process flow that allows for creation of a very steep boron profile in the multiplication region, reducing the fractional acceptor removal and resulting performance degradation. The new LGAD process flow requires a low temperature silicon-silicon wafer bonding process, which is currently under development. TCAD process simulations are used to demonstrate feasibility of the new structure, and TCAD device simulations are used to characterize LGAD performance before and after irradiation.
available system bandwidth. This TDC has a two buffer input quew and a four buffa ouqntt qucuh Af... more available system bandwidth. This TDC has a two buffer input quew and a four buffa ouqntt qucuh Aftw an event is A prototype 64 channel Fastbus TDC built at Fermilab is acqubcd. input buffers can be swapped in about 50 nsec. Two described The module features a full custom CMOS fom hit capability is implemented with 40 tuec double pulse chatmel gad integnuu chip. one level of analog buffering at t-esoIutimt. Only tints fmn hit channels is di&izcd and written the inputs is impkmented cm chip. A four event dce.p output info rhe output queue. Tlti.3 queue allows events to be acquired queue at the bus interface allows * bigb event rate with low and read cut simultaneously. With these hvo queues. both the dead time. Each channel can record up to hvo hits per event cm card digitizing system and tie aatc readout system can be With an occupation rate of 10%. the module can opcmtc at rmtuing at nearly maximum capaeity with vuy low deadtime. 40,ooO events per seccd with dead time on the order o...
CROSS CONNECT SWITCH A reconfigurable memory having M bit lines and a plurality of row lines, whe... more CROSS CONNECT SWITCH A reconfigurable memory having M bit lines and a plurality of row lines, where MZ1. The memory includes an array of memory Storage cells, each memory Storage cell Storing a data value. The data value is read from or into the Storage cells by coupling that data value to one of the bit lines in response to a row control Signal on one of the row lines. A row Select circuit generates the row control Signal on one of the row lines in response to a row address being coupled to the row Select circuit. The row Select circuit includes a memory for Storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of Sense amplifiers, one Such Sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory Storage cells both at power up and run time to detect def...
Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D ... more Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D DRAM will be presented along with the plans (and possibly some results) of further integration with other 3D host logic devices. Additionally, results from several other recent 3D integrations will be reviewed.
Tezzaron has worked for several years in the area of 3D integrated circuit development. During 20... more Tezzaron has worked for several years in the area of 3D integrated circuit development. During 2010, 3 different multiproject wafer runs targeting 2 to 5 layer 3DICs for several different customers were started. Tezzaron's perspective on the results of those runs, issues, and futures will be discussed.
This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology includin... more This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to wafer integration of InP and GaAs with CMOS devices and new work in bonded die to wafer assembly with sub 25um pitch. A manufacturing perspective of the evolving customer requirements and the unique challenges in testing these highly complex devices will be discussed.
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12, 2012
Summary form only given. Moore's law predicted the sustained scaling the semiconductor indust... more Summary form only given. Moore's law predicted the sustained scaling the semiconductor industry has enjoyed for decades, but in the coming decade the limits of physics will force the pace of geometric scaling to slow and perhaps all but stop. In the face of this issue, the electronics industry needs alternatives that can give end consumers the continual increase in function and reduction in cost that they have come to expect. 3D integrated circuits have emerged as the near term solution to mitigate the roll-off of geometric semiconductor scaling. The power of 3D circuit integration comes from its ability to reduce wire length. The ramifications of this are more numerous and powerful than one might initially realize. The shortened wires improve speed and reduce power, but they also allow new combinations of technologies optimized for the performance of specific circuitry. 3D wiring changes alone might provide a 5-30% device improvement, but combining disparate circuit types and using 3D optimized architectures could enable 100-500% improvements. This paper discusses the benefits of 3D and the methods of producing various types of 3D and examines various examples ranging from imagers to exascale computing memories. It also presents an overview of the new requirements that 3D EDA tools must address to effectively handle 3D integration and describes some of the tools that are already available.
Proceedings of the 2011 international symposium on Physical design - ISPD '11, 2011
In this paper, we describe the developments over the past several years in field of 3D integrated... more In this paper, we describe the developments over the past several years in field of 3D integrated circuits. 3D integration offers far greater improvements than traditional semiconductor scaling can provide today. Considered part of the "More Than Moore" category of semiconductor technology, in addition to increasing circuit and system density, 3D integrated circuits can blend a wide range of materials and technologies into a signal polylithic device acting as if these disparate items were truly fabricated together on a single wafer. 3D offers improvement in power, speed, density, cost and reliability, but to access these, new design techniques and system architectures must be used. The paper will review various 3D integration techniques, tool requirements, application of advanced test methodologies, and results.
This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like mater... more This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like materials or components – but also provides information about homogeneous 3D assemblies in combination with other 2D or 3D devices. One example of homogeneous integration is the stacking of memory layers to create a 3D memory device. In such a device, the component layers are usually made of the same material and are often virtually identical in design. This chapter uses 3D DRAM as a reference application.
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