2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019
The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chip... more The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chips to transmit multiple signals the maximum clocking frequency. With the additional multiplexers, this technique dramatically increases system-level routing capability in the FPGA-based emulator. However, the large number of virtual wires in the chip interconnection may impact emulation performance. The system-level FPGA routing tends to connect all virtual wires (signals) and considers emulation performance. At the same time, the challenge for system-level FPGA routing using time division multiplexing lies in the emulation performance.
2011 12th International Symposium on Quality Electronic Design, 2011
Abstract Redundancy removal, ie., identifying and eliminating redundant logic, is an essential op... more Abstract Redundancy removal, ie., identifying and eliminating redundant logic, is an essential optimization strategy for decreasing design area, reducing critical path delay, and simplifying circuit testability analysis. However, redundancy removal strategies invoke ...
Proceedings of the 2009 international symposium on Physical design, 2009
ABSTRACT In modern designs, the delay of a net can vary significantly depending on its routing. T... more ABSTRACT In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by ...
Power is one of the biggest concerns of IC designs today. For consumer electronics the energy con... more Power is one of the biggest concerns of IC designs today. For consumer electronics the energy consumption of the ICs limits the time between charging the batteries. For high-frequency computers the power density of the ICs limits the performance of the ICs. Clock distribution networks typically contribute more than one third of the total power consumption, including both leakage and
International Journal of Foundations of Computer Science, 2006
We present a new abstraction refinement algorithm to better refine the abstract model for formal ... more We present a new abstraction refinement algorithm to better refine the abstract model for formal property verification. In previous work, refinements are selected either based on a set of counter examples of the current abstract model, as in [5, 6, 7, 8, 9, 20, 21], or independent of any counter examples, as in [18]. We (1) introduce a new controllability analysis that is independent of any particular counter examples, (2) apply a new cooperativeness analysis that extracts information from a particular set of counter examples and (3) combine both to better refine the abstract model. We implemented the algorithm and applied it to verify several real-world designs and properties. We compared the algorithm against the abstraction refinement algorithms in [20] and [21] and the interpolation-based reachability analysis in [15]. The experimental results indicate that the new algorithm outperforms the other three algorithms in terms of runtime, abstraction efficiency (as defined in [20]) a...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019
The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chip... more The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chips to transmit multiple signals the maximum clocking frequency. With the additional multiplexers, this technique dramatically increases system-level routing capability in the FPGA-based emulator. However, the large number of virtual wires in the chip interconnection may impact emulation performance. The system-level FPGA routing tends to connect all virtual wires (signals) and considers emulation performance. At the same time, the challenge for system-level FPGA routing using time division multiplexing lies in the emulation performance.
2011 12th International Symposium on Quality Electronic Design, 2011
Abstract Redundancy removal, ie., identifying and eliminating redundant logic, is an essential op... more Abstract Redundancy removal, ie., identifying and eliminating redundant logic, is an essential optimization strategy for decreasing design area, reducing critical path delay, and simplifying circuit testability analysis. However, redundancy removal strategies invoke ...
Proceedings of the 2009 international symposium on Physical design, 2009
ABSTRACT In modern designs, the delay of a net can vary significantly depending on its routing. T... more ABSTRACT In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by ...
Power is one of the biggest concerns of IC designs today. For consumer electronics the energy con... more Power is one of the biggest concerns of IC designs today. For consumer electronics the energy consumption of the ICs limits the time between charging the batteries. For high-frequency computers the power density of the ICs limits the performance of the ICs. Clock distribution networks typically contribute more than one third of the total power consumption, including both leakage and
International Journal of Foundations of Computer Science, 2006
We present a new abstraction refinement algorithm to better refine the abstract model for formal ... more We present a new abstraction refinement algorithm to better refine the abstract model for formal property verification. In previous work, refinements are selected either based on a set of counter examples of the current abstract model, as in [5, 6, 7, 8, 9, 20, 21], or independent of any counter examples, as in [18]. We (1) introduce a new controllability analysis that is independent of any particular counter examples, (2) apply a new cooperativeness analysis that extracts information from a particular set of counter examples and (3) combine both to better refine the abstract model. We implemented the algorithm and applied it to verify several real-world designs and properties. We compared the algorithm against the abstraction refinement algorithms in [20] and [21] and the interpolation-based reachability analysis in [15]. The experimental results indicate that the new algorithm outperforms the other three algorithms in terms of runtime, abstraction efficiency (as defined in [20]) a...
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