Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. S... more Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.
This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112... more This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112, 140, and 168 Gb/s in PAM4, PAM6, and PAM8, respectively. The TX with 1.2-Vppd high-swing driver is implemented in a 7-nm FinFET process. Time domain analysis is performed to compare PAM modulation formats. The power efficiency is 1.5 pJ/b (PAM4) and 1.0 pJ/b (PAM8).
This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 14... more This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).
2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
Recent advances in ADCs have enabled DSP-based equalization (e.g. extensive FFE and DFE) of wirel... more Recent advances in ADCs have enabled DSP-based equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The canonical DFE is challenged by timing closure, and necessary techniques to ease it result in exponential growth in size. As a result, the majority of state-of-the-art DFE implementations have been limited to only 1-2 taps [1–4]. In this paper, a sliding-block DFE (SB-DFE) is introduced that enables pipelining and breaks the barrier to implementing much longer DFEs. Consequently, the DFE length can be extended to encompass all postcursors. Unlike FFEs, DFEs do not amplify noise. Moreover, a long DFE can relax or even remove the postcursor equalization burden on the CTLE and FFE, saving area and power.
This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112... more This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112, 140, and 168 Gb/s in PAM4, PAM6, and PAM8, respectively. The TX with 1.2-Vppd high-swing driver is implemented in a 7-nm FinFET process. Time domain analysis is performed to compare PAM modulation formats. The power efficiency is 1.5 pJ/b (PAM4) and 1.0 pJ/b (PAM8).
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021
This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 14... more This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).
2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019
With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for... more With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2, 4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS SerDes in a system. AMS provides an easier and cheaper approach to implement multi-tap DFEs [3] compared to DSP where it is typically very expensive to implement more than a 1-tap DFE. This paper will show an ADC-DSP SerDes transceiver with a 2-tap DFE is capable of operating error-free over a 38dB link yet having an overall power budget similar to AMS. The same basic SerDes architecture is implemented (Fig. 6.2.1) with minor differences in 16nm and 7nm FinFET, however, power scaling is incorporated into the 7nm version only.
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. S... more Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.
2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion... more DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion loss (IL) with low-to-moderate crosstalk –[2]. At same time, power scaling techniques [3] have closed the energy efficiency gap compared with analog/mixed-signal transceivers on shorter links. Notwithstanding advances in materials and connectors, in large repeater-less backplanes, transceivers are required to operate reliably at 100Gb/s with more than 40dB IL. Furthermore, next generation computing and AI applications require 50Gb/s rates per lane on channels with more than 45dB loss but without the latency of forward error correction (FEC). In this paper we demonstrate a reconfigurable ADC-DSP SerDes capable of operating with BER $\le 1E-05$ at 112Gb/s in PAM-4 or Duo-PAM-4 across a 45dB loss channel, and 58Gb/s PAM-2 at $\lt 1E-15$ over a 52dB loss channel without FEC, while achieving a power efficiency better than 6pJ/b. The SerDes architecture is shown in Fig. 8.4.1 and features extensive power scaling capability.
Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most ... more Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance loss. A nine-tap configuration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-digital signal processing (DSP) four-level pulse amplitude modulation (PAM-4) LR wireline receiver implemented in 7-nm FinFET. The architecture partitions the received signal into overlapping but computationally independent blocks thereby breaking the feedback loop of the DFE and allowing logic pipelining. Unlike existing feedback-breaking techniques, the computational overhead of the SB-DFE can be made arbitrarily small for any tap count—indeed, we show the practicality of SB-DFE implementations exceeding 30 taps. Optimized pipeline cuts are employed to minimize the latency through the SB-DFE while maintaining timing margin. The nine-tap SB-DFE is paired with a five-precursor tap feedforward equalizer (FFE) and compared to a two-tap-DFE 15-tap-FFE reference DSP implemented in the same receiver. A bit error rate of 2 $\\times $ 10−12 is measured over a 36-dB loss channel—at least an order-of-magnitude reduction compared to the reference DSP. Power is reduced by 0.33 pJ/b. DSP gate area is reduced by 30%. Noise tolerance is improved by 0.2-mVRMS. Error-free operation is demonstrated on an RS(544,514) KP4 forward error correction (FEC)-encoded link even when the DFE tap values are manually stressed. Techniques for further reduction in complexity are described.
Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. S... more Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.
This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112... more This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112, 140, and 168 Gb/s in PAM4, PAM6, and PAM8, respectively. The TX with 1.2-Vppd high-swing driver is implemented in a 7-nm FinFET process. Time domain analysis is performed to compare PAM modulation formats. The power efficiency is 1.5 pJ/b (PAM4) and 1.0 pJ/b (PAM8).
This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 14... more This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).
2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
Recent advances in ADCs have enabled DSP-based equalization (e.g. extensive FFE and DFE) of wirel... more Recent advances in ADCs have enabled DSP-based equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The canonical DFE is challenged by timing closure, and necessary techniques to ease it result in exponential growth in size. As a result, the majority of state-of-the-art DFE implementations have been limited to only 1-2 taps [1–4]. In this paper, a sliding-block DFE (SB-DFE) is introduced that enables pipelining and breaks the barrier to implementing much longer DFEs. Consequently, the DFE length can be extended to encompass all postcursors. Unlike FFEs, DFEs do not amplify noise. Moreover, a long DFE can relax or even remove the postcursor equalization burden on the CTLE and FFE, saving area and power.
This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112... more This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112, 140, and 168 Gb/s in PAM4, PAM6, and PAM8, respectively. The TX with 1.2-Vppd high-swing driver is implemented in a 7-nm FinFET process. Time domain analysis is performed to compare PAM modulation formats. The power efficiency is 1.5 pJ/b (PAM4) and 1.0 pJ/b (PAM8).
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021
This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 14... more This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).
2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019
With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for... more With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2, 4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS SerDes in a system. AMS provides an easier and cheaper approach to implement multi-tap DFEs [3] compared to DSP where it is typically very expensive to implement more than a 1-tap DFE. This paper will show an ADC-DSP SerDes transceiver with a 2-tap DFE is capable of operating error-free over a 38dB link yet having an overall power budget similar to AMS. The same basic SerDes architecture is implemented (Fig. 6.2.1) with minor differences in 16nm and 7nm FinFET, however, power scaling is incorporated into the 7nm version only.
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. S... more Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.
2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion... more DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion loss (IL) with low-to-moderate crosstalk –[2]. At same time, power scaling techniques [3] have closed the energy efficiency gap compared with analog/mixed-signal transceivers on shorter links. Notwithstanding advances in materials and connectors, in large repeater-less backplanes, transceivers are required to operate reliably at 100Gb/s with more than 40dB IL. Furthermore, next generation computing and AI applications require 50Gb/s rates per lane on channels with more than 45dB loss but without the latency of forward error correction (FEC). In this paper we demonstrate a reconfigurable ADC-DSP SerDes capable of operating with BER $\le 1E-05$ at 112Gb/s in PAM-4 or Duo-PAM-4 across a 45dB loss channel, and 58Gb/s PAM-2 at $\lt 1E-15$ over a 52dB loss channel without FEC, while achieving a power efficiency better than 6pJ/b. The SerDes architecture is shown in Fig. 8.4.1 and features extensive power scaling capability.
Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most ... more Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance loss. A nine-tap configuration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-digital signal processing (DSP) four-level pulse amplitude modulation (PAM-4) LR wireline receiver implemented in 7-nm FinFET. The architecture partitions the received signal into overlapping but computationally independent blocks thereby breaking the feedback loop of the DFE and allowing logic pipelining. Unlike existing feedback-breaking techniques, the computational overhead of the SB-DFE can be made arbitrarily small for any tap count—indeed, we show the practicality of SB-DFE implementations exceeding 30 taps. Optimized pipeline cuts are employed to minimize the latency through the SB-DFE while maintaining timing margin. The nine-tap SB-DFE is paired with a five-precursor tap feedforward equalizer (FFE) and compared to a two-tap-DFE 15-tap-FFE reference DSP implemented in the same receiver. A bit error rate of 2 $\\times $ 10−12 is measured over a 36-dB loss channel—at least an order-of-magnitude reduction compared to the reference DSP. Power is reduced by 0.33 pJ/b. DSP gate area is reduced by 30%. Noise tolerance is improved by 0.2-mVRMS. Error-free operation is demonstrated on an RS(544,514) KP4 forward error correction (FEC)-encoded link even when the DFE tap values are manually stressed. Techniques for further reduction in complexity are described.
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Papers by Peter Krotnev