A method proposed in this is is to design carry look ahead adders using SCMOS technology, also an... more A method proposed in this is is to design carry look ahead adders using SCMOS technology, also analyze the effect of various parameters on the characteristics of adders, using 50 nm, spice model for CMOS technology. The design was implemented for 16 bit and then extended for 32 bit also. Here parameters are computed and response curves are computed between all characteristics, DC and transient characteristics. The design and simulations are carried out to achieve these values approximately. Design will be carried out in either Electric CAD or Xilinx. Simulation results are verified using Modelsim and LTSpice. The DRC, LVS/NCC, transient checks are performed in the proposed design. Noise analysis is also done. In comparison with the existing full adder designs, the present implementation will offer significant improvement in terms of frequency.
This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesse... more This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.
international journal of engineering trends and technology, 2014
In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissi... more In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissipation plays important role in designing of any digital circuit. In earlier many approaches were used to reduce power dissipation. Reversible logic design can also be used for same objective. This approach gaining importance day by day. Arithmetic logic unit is very important part of central processing unit. So it must be fast in term of computations and should dissipate less power. Here a technique is discussed for designing arithmetic and logic unit with the use of reversible gates. Modules are designed using VHDL. Synthesis and simulation is carried out on Xilinx plan ahead 14.4.
Reversible logic is promising as it is able to compute with various applications in very low powe... more Reversible logic is promising as it is able to compute with various applications in very low power like nano- computing for example quantum computing. Reversible circuits are like conventional circuits despite they are build from reversible gates. Reversible circuits, have single, one-to-one mapping between the input and output vectors.Thus all output vectors are permutations of input vectors. A concise review of reversible logic gates basics will be studied. The basic reversible logic gates need to be optimized in reversible logic design and synthesis. Reversible gates need steady inputs for configuration of gate functions and junk outputs that helps in keeping reversibility. Therefore, it is very important to lessen the parameters such as junk bytes, quantum cost and delay in the scheming of reversible circuits. As reversible circuits have tremendous applications in a vairety of emerging technologies such as quantum computing and quantum dot. Consequently this research work would ...
The integrated circuits that have memories, a major share of total circuit power is required by t... more The integrated circuits that have memories, a major share of total circuit power is required by the memory architecture of the circuit. With the day-to-day changing circuit designs, the need to store increasing amount of processing data has resulted in the growing memory size in an integrated circuit. Most of the memory data remains un-altered during the memory data handling operation. The stored data is thus affected by the sub-threshold leakage power / current that leads to the degradation of data signal quality. The data integrity is maintained using a feedback path / architecture in SRAM memory architecture. Still, the amount of power loss due to leakage contributes a major part of the total power loss of the integrated circuit. This loss increases with the decrease in the physical feature size of the component / transistors. A low power system offers the benefits like device portability, long battery life, good performance criteria, etc. Today's increasing data handling req...
Low power is an imperative requirement for portable multimedia devices employing various signal p... more Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. This paper contributes to better understanding of the behaviour of single-bit full adder cells when lowest power-delay products are essential. Four single-bit full adder cells have been implemented in Cadence tool suit and simulated using 180nm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power consumption. The method combines the simple measurement technique for obtaining accurate time-delays and power consumption of a cell, and the transistor resizing technique that allows ...
In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The pro... more In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The proposed Multiplier Algorithm takes reduced area than the previous one and the significant delay is also lower than the previous designs. The number of slices in the previous designs is 648 and in our proposed Dadda Multiplier architecture utilizes only 402 slices then area is reduced up to 30%. As shown in the design as well as the simulation results the proposed Multiplier architecture area as well as delay is better.
International Journal of Computer Science and Informatics, 2014
This paper deals with the study of Independent Component Analysis. Independent Component Analysis... more This paper deals with the study of Independent Component Analysis. Independent Component Analysis is basically a method which is used to implement the concept of Blind Source Separation. Blind Source Separation is a technique which is used to extract set of source signal from set of their mixed source signals. The various techniques which are used for implementing Blind Source Separation totally depends upon the properties and the characteristics of original sources. Also there are many fields nowadays in which Independent Component Analysis is widely used. This paper deals with the theoretical concepts of Independent Component Analysis, its principles and its widely used applications.
Transistor density on integrated circuit doubles every two year. For decades, Intel has met this ... more Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub–circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built–In–Self–Test (BIST) technique has emerged as a cheap alternative.
Although dental implantology had evolved over a number of years, many dental surgeons are unaware... more Although dental implantology had evolved over a number of years, many dental surgeons are unaware of the concept of immediate loading with the use of one-piece implant that began in the early 1960s. The goal of successful prosthodontics rehabilitation is to provide function, esthetics, and comfort to the patient. The aim of this literature is to provide an overview of one-piece implant, with its advantages and disadvantages over conventional two-piece implant. Immediate prosthetic of a one-piece system allows for a better tissue healing and better adhesion of gingival mucosa to form a collar which is healthy and adherent to the implant, avoiding a second surgical procedure, and also includes a very important aspect esthetics. This article describes a case report of immediate loading with single-piece implant following extraction.
2011 IEEE Recent Advances in Intelligent Computational Systems, 2011
Built-in self-test techniques have been widely researched and adopted for reasons of improvements... more Built-in self-test techniques have been widely researched and adopted for reasons of improvements in test time and test cost, reduction in test resources required for test of large chips with embedded cores, and for field testability. While the adoption of these techniques is becoming prevalent, there continue to be challenges in making BIST solutions comprehensive to meet several design and application constraints. This paper describes the use of BIST implementations for self-test of a communication system, to support field testability. Novel aspects of this solution include (i) full off-line testing of the link and system, (ii) partial online testing, and (iii) support for various network management functions.
Previous work suggested the potential utility of therapy with a monoclonal antibody (Mab) to inte... more Previous work suggested the potential utility of therapy with a monoclonal antibody (Mab) to intercellular adhesion molecule-1 (ICAM-1; CD54) in patients with longstanding rheumatoid arthritis (RA). Immunomodulatory interventions, including adhesion receptor directed therapies, might be expected to have greater efficacy in patients with less established or less aggressive disease. Therefore, we assessed the efficacy and safety of an anti-ICAM-1 Mab in patients with early RA. An open label study of a 5 day infusion of an anti-ICAM-1 Mab in 10 patients with early or indolent RA was conducted. These patients were defined as having previously used < or = 1 disease modifying antirheumatic drug. Based on composite criteria, 7/10 patients had a marked or moderate response to therapy at one month of followup. Clinical benefit was sustained through 2 months for 5/10 patients and 3/10 had extended benefit (11, 8, and > 7 months). Clinical benefit was more likely to be obtained in patien...
A method proposed in this is is to design carry look ahead adders using SCMOS technology, also an... more A method proposed in this is is to design carry look ahead adders using SCMOS technology, also analyze the effect of various parameters on the characteristics of adders, using 50 nm, spice model for CMOS technology. The design was implemented for 16 bit and then extended for 32 bit also. Here parameters are computed and response curves are computed between all characteristics, DC and transient characteristics. The design and simulations are carried out to achieve these values approximately. Design will be carried out in either Electric CAD or Xilinx. Simulation results are verified using Modelsim and LTSpice. The DRC, LVS/NCC, transient checks are performed in the proposed design. Noise analysis is also done. In comparison with the existing full adder designs, the present implementation will offer significant improvement in terms of frequency.
This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesse... more This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.
international journal of engineering trends and technology, 2014
In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissi... more In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissipation plays important role in designing of any digital circuit. In earlier many approaches were used to reduce power dissipation. Reversible logic design can also be used for same objective. This approach gaining importance day by day. Arithmetic logic unit is very important part of central processing unit. So it must be fast in term of computations and should dissipate less power. Here a technique is discussed for designing arithmetic and logic unit with the use of reversible gates. Modules are designed using VHDL. Synthesis and simulation is carried out on Xilinx plan ahead 14.4.
Reversible logic is promising as it is able to compute with various applications in very low powe... more Reversible logic is promising as it is able to compute with various applications in very low power like nano- computing for example quantum computing. Reversible circuits are like conventional circuits despite they are build from reversible gates. Reversible circuits, have single, one-to-one mapping between the input and output vectors.Thus all output vectors are permutations of input vectors. A concise review of reversible logic gates basics will be studied. The basic reversible logic gates need to be optimized in reversible logic design and synthesis. Reversible gates need steady inputs for configuration of gate functions and junk outputs that helps in keeping reversibility. Therefore, it is very important to lessen the parameters such as junk bytes, quantum cost and delay in the scheming of reversible circuits. As reversible circuits have tremendous applications in a vairety of emerging technologies such as quantum computing and quantum dot. Consequently this research work would ...
The integrated circuits that have memories, a major share of total circuit power is required by t... more The integrated circuits that have memories, a major share of total circuit power is required by the memory architecture of the circuit. With the day-to-day changing circuit designs, the need to store increasing amount of processing data has resulted in the growing memory size in an integrated circuit. Most of the memory data remains un-altered during the memory data handling operation. The stored data is thus affected by the sub-threshold leakage power / current that leads to the degradation of data signal quality. The data integrity is maintained using a feedback path / architecture in SRAM memory architecture. Still, the amount of power loss due to leakage contributes a major part of the total power loss of the integrated circuit. This loss increases with the decrease in the physical feature size of the component / transistors. A low power system offers the benefits like device portability, long battery life, good performance criteria, etc. Today's increasing data handling req...
Low power is an imperative requirement for portable multimedia devices employing various signal p... more Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. This paper contributes to better understanding of the behaviour of single-bit full adder cells when lowest power-delay products are essential. Four single-bit full adder cells have been implemented in Cadence tool suit and simulated using 180nm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power consumption. The method combines the simple measurement technique for obtaining accurate time-delays and power consumption of a cell, and the transistor resizing technique that allows ...
In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The pro... more In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The proposed Multiplier Algorithm takes reduced area than the previous one and the significant delay is also lower than the previous designs. The number of slices in the previous designs is 648 and in our proposed Dadda Multiplier architecture utilizes only 402 slices then area is reduced up to 30%. As shown in the design as well as the simulation results the proposed Multiplier architecture area as well as delay is better.
International Journal of Computer Science and Informatics, 2014
This paper deals with the study of Independent Component Analysis. Independent Component Analysis... more This paper deals with the study of Independent Component Analysis. Independent Component Analysis is basically a method which is used to implement the concept of Blind Source Separation. Blind Source Separation is a technique which is used to extract set of source signal from set of their mixed source signals. The various techniques which are used for implementing Blind Source Separation totally depends upon the properties and the characteristics of original sources. Also there are many fields nowadays in which Independent Component Analysis is widely used. This paper deals with the theoretical concepts of Independent Component Analysis, its principles and its widely used applications.
Transistor density on integrated circuit doubles every two year. For decades, Intel has met this ... more Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub–circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built–In–Self–Test (BIST) technique has emerged as a cheap alternative.
Although dental implantology had evolved over a number of years, many dental surgeons are unaware... more Although dental implantology had evolved over a number of years, many dental surgeons are unaware of the concept of immediate loading with the use of one-piece implant that began in the early 1960s. The goal of successful prosthodontics rehabilitation is to provide function, esthetics, and comfort to the patient. The aim of this literature is to provide an overview of one-piece implant, with its advantages and disadvantages over conventional two-piece implant. Immediate prosthetic of a one-piece system allows for a better tissue healing and better adhesion of gingival mucosa to form a collar which is healthy and adherent to the implant, avoiding a second surgical procedure, and also includes a very important aspect esthetics. This article describes a case report of immediate loading with single-piece implant following extraction.
2011 IEEE Recent Advances in Intelligent Computational Systems, 2011
Built-in self-test techniques have been widely researched and adopted for reasons of improvements... more Built-in self-test techniques have been widely researched and adopted for reasons of improvements in test time and test cost, reduction in test resources required for test of large chips with embedded cores, and for field testability. While the adoption of these techniques is becoming prevalent, there continue to be challenges in making BIST solutions comprehensive to meet several design and application constraints. This paper describes the use of BIST implementations for self-test of a communication system, to support field testability. Novel aspects of this solution include (i) full off-line testing of the link and system, (ii) partial online testing, and (iii) support for various network management functions.
Previous work suggested the potential utility of therapy with a monoclonal antibody (Mab) to inte... more Previous work suggested the potential utility of therapy with a monoclonal antibody (Mab) to intercellular adhesion molecule-1 (ICAM-1; CD54) in patients with longstanding rheumatoid arthritis (RA). Immunomodulatory interventions, including adhesion receptor directed therapies, might be expected to have greater efficacy in patients with less established or less aggressive disease. Therefore, we assessed the efficacy and safety of an anti-ICAM-1 Mab in patients with early RA. An open label study of a 5 day infusion of an anti-ICAM-1 Mab in 10 patients with early or indolent RA was conducted. These patients were defined as having previously used < or = 1 disease modifying antirheumatic drug. Based on composite criteria, 7/10 patients had a marked or moderate response to therapy at one month of followup. Clinical benefit was sustained through 2 months for 5/10 patients and 3/10 had extended benefit (11, 8, and > 7 months). Clinical benefit was more likely to be obtained in patien...
Uploads
Papers by RITA JAIN