2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015
The CMOS based memories are facing major issues with technology scaling, such as decreased reliab... more The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.
The relentless decrease in feature size and the increase of density requirements in Integrated Ci... more The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional integrated circuits (3D ICs). Several possibilities have been presented, but one of the clearest options is based on the use of Though-Silicon Vias (TSV) connections. The benefits and disadvantages that TSV inclusion adds to design need further studies. The implementation of these vertical vias can affect the general performance of circuit and thus changing verification strategies or testing processes. In this paper, the electrical effect of open defects affecting TSVs in a 3D SRAM module is presented. Analytical expressions are presented to provide designers a tool to improve circuit features and help them in the analysis of how TSV implementation can affect a SRAM array design
In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpr... more In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal.
Abstract—An Interconnect full open defect breaks the connec-tion between the driver and the gate ... more Abstract—An Interconnect full open defect breaks the connec-tion between the driver and the gate terminals of downstream tran-sistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the be-havior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The oc-currence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are an-alyzed and...
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is use... more Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017
Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming in... more Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.
2017 22nd IEEE European Test Symposium (ETS), 2017
In this paper we propose a methodology for reliability evaluation, failure prediction, and failur... more In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.
2016 Conference on Design of Circuits and Integrated Systems (DCIS), 2016
Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile ... more Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs still poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write operation of two parallel cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF) like primitive is implemented based on modified 1 transistor-1 resistor (1T1R) array structure.
The ubiquitous use of critical and private data in electronic format requires reliable and secure... more The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, t...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Intragate open defects are responsible for a significant percentage of defects in present technol... more Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.
ABSTRACT Full open defects on interconnect lines cause broken wires to become floating. The volta... more ABSTRACT Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.
2015 20th IEEE European Test Symposium (ETS), 2015
One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Rando... more One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper we estimate the STT-MRAM cell reliability under fabrication-and aging-induced process variability by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and as a result, we propose a power-and agingaware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation) but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis the appropriate value of this control voltage is determined.
Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improv... more Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
The rapid development of low power, high density, high performance SoCs has pushed the embedded m... more The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability making robustness evaluation an important concern. In this paper, we provide new metrics for robustness prediction of an STT-MRAM memory cell. Independent Robustness Margin metrics are defined for Read Operation and Write Operation based on the electrical characteristics of the memory cell and the fabrication induced variability. These metrics are used to estimate the extreme parameter variation causing the cell failure, Current Noise Margins and the Failure Probability of the STT-MRAM cell.
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 2004
Built-in self-test (BIST) strategies require the implementation of efficient test pattern generat... more Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) in order to excite and observe the potential faults of the circuit. Arithmetic additive TPGs (AdTPG) allow the reuse of existing internal datapaths to perform this operation without a penalty in the circuit area. As in pseudo-random generators, AdTPGs need reseeding to efficiently cover hard-to-detect faults. The test vectors targeting hard-todetect faults are often difficult to be obtained from a simple iterative addition operation. In this paper, a strategy to generate the reseeding for an AdTPG based on a standard ALU is presented. The methodology benefits from the existence of don't-cares in the test vectors and from the insertion of dummy vectors in the test sequence. Thanks to this, a reduction of the memory requirements and the test length is achieved.
2014 19th IEEE European Test Symposium (ETS), 2014
Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high b... more Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 k. Experimental work on a 65-nm IC also corroborates the detection capability of the proposal. Index Terms-Design for testability, duty cycle (DC), resistive open defect, three-dimensional integrated circuit (3-D IC), through-silicon via (TSV), TSV testing. I. INTRODUCTION T HE semiconductor industry is continuously demanding products with higher integration density and performance, lower power consumption, and reduced cost. Among the different alternatives, three-dimensional integrated circuits (3-D ICs) have developed as a solution to meet such demands [1]. A 3-D IC integrates a vertical stack of tiers of thinned 2-D ICs into a single package interconnected by means of through-silicon vias (TSVs). A TSV is a vertical via formed between tiers through silicon or oxide layers. TSVs reduce interconnectivity length, permit higher density, and generate low-capacity interconnects compared to traditional wire bonds. Both vertical and horizontal interconnections in TSV-based 3-D ICs are susceptible to a variety of manufacturing defects. However, the special features of 3-D ICs induce particular test
Comparison between current and voltage testing in a scan-path flip-flop affected by single bridgi... more Comparison between current and voltage testing in a scan-path flip-flop affected by single bridging defects is presented. Defects obtained by inductive fault analysis (IFA) have been classified depending on the location within the scan cell and its electrical behaviour has been simulated using HSPICE. Current (Iddq) testing of zero resistance bridges covers only 92% of the realistic bridges obtained by
Abstract Full open defects on the interconnect lines cause the broken wires to become floating. ... more Abstract Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream ...
2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015
The CMOS based memories are facing major issues with technology scaling, such as decreased reliab... more The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.
The relentless decrease in feature size and the increase of density requirements in Integrated Ci... more The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional integrated circuits (3D ICs). Several possibilities have been presented, but one of the clearest options is based on the use of Though-Silicon Vias (TSV) connections. The benefits and disadvantages that TSV inclusion adds to design need further studies. The implementation of these vertical vias can affect the general performance of circuit and thus changing verification strategies or testing processes. In this paper, the electrical effect of open defects affecting TSVs in a 3D SRAM module is presented. Analytical expressions are presented to provide designers a tool to improve circuit features and help them in the analysis of how TSV implementation can affect a SRAM array design
In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpr... more In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal.
Abstract—An Interconnect full open defect breaks the connec-tion between the driver and the gate ... more Abstract—An Interconnect full open defect breaks the connec-tion between the driver and the gate terminals of downstream tran-sistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the be-havior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The oc-currence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are an-alyzed and...
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is use... more Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017
Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming in... more Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.
2017 22nd IEEE European Test Symposium (ETS), 2017
In this paper we propose a methodology for reliability evaluation, failure prediction, and failur... more In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.
2016 Conference on Design of Circuits and Integrated Systems (DCIS), 2016
Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile ... more Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs still poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write operation of two parallel cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF) like primitive is implemented based on modified 1 transistor-1 resistor (1T1R) array structure.
The ubiquitous use of critical and private data in electronic format requires reliable and secure... more The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, t...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Intragate open defects are responsible for a significant percentage of defects in present technol... more Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.
ABSTRACT Full open defects on interconnect lines cause broken wires to become floating. The volta... more ABSTRACT Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.
2015 20th IEEE European Test Symposium (ETS), 2015
One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Rando... more One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper we estimate the STT-MRAM cell reliability under fabrication-and aging-induced process variability by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and as a result, we propose a power-and agingaware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation) but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis the appropriate value of this control voltage is determined.
Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improv... more Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
The rapid development of low power, high density, high performance SoCs has pushed the embedded m... more The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability making robustness evaluation an important concern. In this paper, we provide new metrics for robustness prediction of an STT-MRAM memory cell. Independent Robustness Margin metrics are defined for Read Operation and Write Operation based on the electrical characteristics of the memory cell and the fabrication induced variability. These metrics are used to estimate the extreme parameter variation causing the cell failure, Current Noise Margins and the Failure Probability of the STT-MRAM cell.
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 2004
Built-in self-test (BIST) strategies require the implementation of efficient test pattern generat... more Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) in order to excite and observe the potential faults of the circuit. Arithmetic additive TPGs (AdTPG) allow the reuse of existing internal datapaths to perform this operation without a penalty in the circuit area. As in pseudo-random generators, AdTPGs need reseeding to efficiently cover hard-to-detect faults. The test vectors targeting hard-todetect faults are often difficult to be obtained from a simple iterative addition operation. In this paper, a strategy to generate the reseeding for an AdTPG based on a standard ALU is presented. The methodology benefits from the existence of don't-cares in the test vectors and from the insertion of dummy vectors in the test sequence. Thanks to this, a reduction of the memory requirements and the test length is achieved.
2014 19th IEEE European Test Symposium (ETS), 2014
Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high b... more Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 k. Experimental work on a 65-nm IC also corroborates the detection capability of the proposal. Index Terms-Design for testability, duty cycle (DC), resistive open defect, three-dimensional integrated circuit (3-D IC), through-silicon via (TSV), TSV testing. I. INTRODUCTION T HE semiconductor industry is continuously demanding products with higher integration density and performance, lower power consumption, and reduced cost. Among the different alternatives, three-dimensional integrated circuits (3-D ICs) have developed as a solution to meet such demands [1]. A 3-D IC integrates a vertical stack of tiers of thinned 2-D ICs into a single package interconnected by means of through-silicon vias (TSVs). A TSV is a vertical via formed between tiers through silicon or oxide layers. TSVs reduce interconnectivity length, permit higher density, and generate low-capacity interconnects compared to traditional wire bonds. Both vertical and horizontal interconnections in TSV-based 3-D ICs are susceptible to a variety of manufacturing defects. However, the special features of 3-D ICs induce particular test
Comparison between current and voltage testing in a scan-path flip-flop affected by single bridgi... more Comparison between current and voltage testing in a scan-path flip-flop affected by single bridging defects is presented. Defects obtained by inductive fault analysis (IFA) have been classified depending on the location within the scan cell and its electrical behaviour has been simulated using HSPICE. Current (Iddq) testing of zero resistance bridges covers only 92% of the realistic bridges obtained by
Abstract Full open defects on the interconnect lines cause the broken wires to become floating. ... more Abstract Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream ...
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Papers by R. Rodriguez