Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited b... more Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited by them when employed in circuits for microwave and RF applications. In this work a junctionless surrounded gate graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyse its linearity performance with the help of ATLAS tool of technology computer aided design (TCAD). The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits (FOMs) such as higher order tranconductances (Gm1 ,Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB– compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in the view of the compression point in comparison to JLSG MOSFET before threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC M...
This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different... more This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enh... more This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the ... more A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(gm) transconductancegeneration factor(TGF), intrinsic gain (gm/gds) output resistance (R0) unity gain cut-off frequency (fT) and Maximum Frequency of Oscillations (fmax) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.
Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have b... more Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result:: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred t...
The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxi... more The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect...
In this paper, the analog/radio frequency and linearity performance of staggered heterojunction n... more In this paper, the analog/radio frequency and linearity performance of staggered heterojunction nanowire tunnel FET is studied and compared with Si and InAs based NW TFET of same dimension. Different analog/RadioFrequency and linearity parameters like transconductance (gm), intrinsic gain (gmR0), cut-off frequency (fT), as well as 1-dB compression point has been studied. There is a better enhancement in the analog/RF performance obtained from heterojunction NW TFET over Si and InAs TFET. To improve ION and subthreshold swing, a considerable advance in the analog/RadioFrequency performance parameters obtain by the HETJ Nanowire TFET in comparision to Si and InAs Nanowire tunnel FET for use in analog/mixed signal low power applications is reported. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, better linearity performance as compared to Si and InAs TFET.
With time the design of RF and Analog application based circuits in MOSFET industry is changing a... more With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(\mathrm{g}_{\mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(\mathrm{R}_{\mathrm{o}\mathrm{u}\mathrm{t}})$, cut-off frequency $(\mathrm{f}_{\mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\mathrm{d}})$, maximum frequency $(\mathrm{f}_{\max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.
2019 Devices for Integrated Circuit (DevIC), Mar 1, 2019
In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect... more In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO2 and the other as high-K i.e- HfO2. Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.
Facta universitatis - series: Electronics and Energetics
This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the p... more This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is...
In this paper, the performance of FinFET has been examined by changing the fin width which affect... more In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (gm), cutoff frequency (fT), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and gm show maximum value, and at medium value of oxide layer width fT and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.
The modern electronics gadget has influenced tremendously every aspects of life. The demand to ad... more The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.
ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019
In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual ... more In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual Metals and Single Metal Gate with respect to different device parameters. The conclusion derived from the investigation reveals that DIBL can be suppressed and transportation capability of carrier can be improved by combining the advantages of junction-less architecture, gate terminal with three different material, and Cylindrical Surrounding Gate. We explore the radio frequency (RF) performance for JLTMCSG MOSFET taking in to account various figure of merits (FOMs) such as cutoff frequency fT, C-V curve, current gain, unilateral power gain and the simulated results are compared with JLDMCSG MOSFET.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis... more In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (g<inf>m</inf>), Output resistance (R<inf>OUT</inf>), Intrinsic Gain (g<inf>m</inf>R<inf>out</inf>), Transconductance Generation factor (g<inf>m</inf>/I<inf>D</inf>), gate capacitance, cutoff frequency(f<inf>T</inf>), maximum frequency of oscillation (f<inf>max</inf>), Gain Bandwidth Product (GBW), VIP2, VIP<inf>3</inf>and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterost...
Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited b... more Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited by them when employed in circuits for microwave and RF applications. In this work a junctionless surrounded gate graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyse its linearity performance with the help of ATLAS tool of technology computer aided design (TCAD). The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits (FOMs) such as higher order tranconductances (Gm1 ,Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB– compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in the view of the compression point in comparison to JLSG MOSFET before threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC M...
This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different... more This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enh... more This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the ... more A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(gm) transconductancegeneration factor(TGF), intrinsic gain (gm/gds) output resistance (R0) unity gain cut-off frequency (fT) and Maximum Frequency of Oscillations (fmax) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.
Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have b... more Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result:: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred t...
The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxi... more The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect...
In this paper, the analog/radio frequency and linearity performance of staggered heterojunction n... more In this paper, the analog/radio frequency and linearity performance of staggered heterojunction nanowire tunnel FET is studied and compared with Si and InAs based NW TFET of same dimension. Different analog/RadioFrequency and linearity parameters like transconductance (gm), intrinsic gain (gmR0), cut-off frequency (fT), as well as 1-dB compression point has been studied. There is a better enhancement in the analog/RF performance obtained from heterojunction NW TFET over Si and InAs TFET. To improve ION and subthreshold swing, a considerable advance in the analog/RadioFrequency performance parameters obtain by the HETJ Nanowire TFET in comparision to Si and InAs Nanowire tunnel FET for use in analog/mixed signal low power applications is reported. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, better linearity performance as compared to Si and InAs TFET.
With time the design of RF and Analog application based circuits in MOSFET industry is changing a... more With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(\mathrm{g}_{\mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(\mathrm{R}_{\mathrm{o}\mathrm{u}\mathrm{t}})$, cut-off frequency $(\mathrm{f}_{\mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\mathrm{d}})$, maximum frequency $(\mathrm{f}_{\max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.
2019 Devices for Integrated Circuit (DevIC), Mar 1, 2019
In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect... more In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO2 and the other as high-K i.e- HfO2. Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.
Facta universitatis - series: Electronics and Energetics
This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the p... more This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is...
In this paper, the performance of FinFET has been examined by changing the fin width which affect... more In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (gm), cutoff frequency (fT), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and gm show maximum value, and at medium value of oxide layer width fT and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.
The modern electronics gadget has influenced tremendously every aspects of life. The demand to ad... more The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.
ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management, 2019
In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual ... more In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual Metals and Single Metal Gate with respect to different device parameters. The conclusion derived from the investigation reveals that DIBL can be suppressed and transportation capability of carrier can be improved by combining the advantages of junction-less architecture, gate terminal with three different material, and Cylindrical Surrounding Gate. We explore the radio frequency (RF) performance for JLTMCSG MOSFET taking in to account various figure of merits (FOMs) such as cutoff frequency fT, C-V curve, current gain, unilateral power gain and the simulated results are compared with JLDMCSG MOSFET.
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis... more In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (g<inf>m</inf>), Output resistance (R<inf>OUT</inf>), Intrinsic Gain (g<inf>m</inf>R<inf>out</inf>), Transconductance Generation factor (g<inf>m</inf>/I<inf>D</inf>), gate capacitance, cutoff frequency(f<inf>T</inf>), maximum frequency of oscillation (f<inf>max</inf>), Gain Bandwidth Product (GBW), VIP2, VIP<inf>3</inf>and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterost...
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Papers by SUDHANSU BISWAL