2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination wit... more ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.
ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D me... more ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination wit... more ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.
ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D me... more ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.
2014 IEEE 6th International Memory Workshop (IMW), 2014
ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni chan... more ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.
2014 IEEE 6th International Memory Workshop (IMW), 2014
ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni chan... more ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D ... more ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D ... more ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
The deposition and film properties for Silcore®-based silicon film deposition, both undoped and d... more The deposition and film properties for Silcore®-based silicon film deposition, both undoped and doped, are discussed for two different hardware configurations, a vertical furnace and a single wafer reactor. Silcore chemistry provides an alternative means of silicon film deposition as compared to traditional silane chemistry, with the key advantages being the lower deposition temperature regime achievable and smoother resulting silicon films.
The deposition and film properties for Silcore®-based silicon film deposition, both undoped and d... more The deposition and film properties for Silcore®-based silicon film deposition, both undoped and doped, are discussed for two different hardware configurations, a vertical furnace and a single wafer reactor. Silcore chemistry provides an alternative means of silicon film deposition as compared to traditional silane chemistry, with the key advantages being the lower deposition temperature regime achievable and smoother resulting silicon films.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and b... more ABSTRACT When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and beyond, the main challenge is the electrical interference between adjacent cells. This can be drastically reduced by thinning the FG below 20 nm. For the 43 nm-node, 60 nm thick FG layers are already used [1]. In this paper we present, based on ASMpsilas Silcorereg precursor for silicon deposition, a proof-of-concept that scaling down the floating gate thickness to 15 nm has no impact on the memory operation.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination wit... more ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.
ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D me... more ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination wit... more ABSTRACT A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.
ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D me... more ABSTRACT The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.
2014 IEEE 6th International Memory Workshop (IMW), 2014
ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni chan... more ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.
2014 IEEE 6th International Memory Workshop (IMW), 2014
ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni chan... more ABSTRACT Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D ... more ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
2011 3rd IEEE International Memory Workshop (IMW), 2011
ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D ... more ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
The deposition and film properties for Silcore®-based silicon film deposition, both undoped and d... more The deposition and film properties for Silcore®-based silicon film deposition, both undoped and doped, are discussed for two different hardware configurations, a vertical furnace and a single wafer reactor. Silcore chemistry provides an alternative means of silicon film deposition as compared to traditional silane chemistry, with the key advantages being the lower deposition temperature regime achievable and smoother resulting silicon films.
The deposition and film properties for Silcore®-based silicon film deposition, both undoped and d... more The deposition and film properties for Silcore®-based silicon film deposition, both undoped and doped, are discussed for two different hardware configurations, a vertical furnace and a single wafer reactor. Silcore chemistry provides an alternative means of silicon film deposition as compared to traditional silane chemistry, with the key advantages being the lower deposition temperature regime achievable and smoother resulting silicon films.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
ABSTRACT When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and b... more ABSTRACT When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and beyond, the main challenge is the electrical interference between adjacent cells. This can be drastically reduced by thinning the FG below 20 nm. For the 43 nm-node, 60 nm thick FG layers are already used [1]. In this paper we present, based on ASMpsilas Silcorereg precursor for silicon deposition, a proof-of-concept that scaling down the floating gate thickness to 15 nm has no impact on the memory operation.
Uploads
Papers by Steven Van Aerde