2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008
As digital circuits grow in gate count so does the data volume required for manufacturing test. T... more As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
Supply current and power dissipation during scan based test may be much higher than during normal... more Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008
As digital circuits grow in gate count so does the data volume required for manufacturing test. T... more As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
Supply current and power dissipation during scan based test may be much higher than during normal... more Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and
Uploads