ABSTRACT As research on developing assertion languages for the AMS domain gains in momentum, it i... more ABSTRACT As research on developing assertion languages for the AMS domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like PSL and SVA into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper we show that by using auxiliary forms of formal specifications such as abstract state machines and real valued functions as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. This approach leverages the growing adoption of AMS behavioral modeling in the industry. The paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
In verification of Analog and Mixed-Signal (AMS) designs, considerable efforts are being given no... more In verification of Analog and Mixed-Signal (AMS) designs, considerable efforts are being given now days towards extending assertion languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) to capture mixed-signal behaviors and verify them on mixed-signal design at run-time. In SVA and PSL the temporal properties are written on boolean valued signals only, whereas in the AMS extensions we intend to handle the real valued variables (like voltages, currents etc) by encapsulating them in terms of analog predicates. In this paper we discuss how certain complex mixed-signal properties can be encoded with the help of local variables and describe a methodology for dynamically verifying such AMS properties by mapping them into SVA properties. We demonstrate the proof of concept using our prototype toolkit which parses the AMS properties involving local variables and generates corresponding equivalent SVA properties and Verilog-AMS monitors to verify them dynamically using Synopsys' mixed-signal simulator Nanosim-VCS along with SVA checker.
ABSTRACT As research on developing assertion languages for the AMS domain gains in momentum, it i... more ABSTRACT As research on developing assertion languages for the AMS domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like PSL and SVA into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper we show that by using auxiliary forms of formal specifications such as abstract state machines and real valued functions as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. This approach leverages the growing adoption of AMS behavioral modeling in the industry. The paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
In verification of Analog and Mixed-Signal (AMS) designs, considerable efforts are being given no... more In verification of Analog and Mixed-Signal (AMS) designs, considerable efforts are being given now days towards extending assertion languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) to capture mixed-signal behaviors and verify them on mixed-signal design at run-time. In SVA and PSL the temporal properties are written on boolean valued signals only, whereas in the AMS extensions we intend to handle the real valued variables (like voltages, currents etc) by encapsulating them in terms of analog predicates. In this paper we discuss how certain complex mixed-signal properties can be encoded with the help of local variables and describe a methodology for dynamically verifying such AMS properties by mapping them into SVA properties. We demonstrate the proof of concept using our prototype toolkit which parses the AMS properties involving local variables and generates corresponding equivalent SVA properties and Verilog-AMS monitors to verify them dynamically using Synopsys' mixed-signal simulator Nanosim-VCS along with SVA checker.
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Papers by Subhankar Mukherjee