This paper presents a case study of worst case timing analysis for a RISC processor. The target m... more This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine that is built based on the extended timing schema approach. 1 Introduction Calculating tight and safe WCET (Worst Case Execution Time) bounds is an important research topic in the real-time com...
Recent progress in worst case timing analysis of programs has made it possible to perform accurat... more Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessary when a RISC processor is used as the target processor of a real-time system. However, there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer-based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). This paper proposes two techniques to...
Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054), 1999
ABSTRACT To predict the worst case execution time (WCET) of real-time tasks, we should consider v... more ABSTRACT To predict the worst case execution time (WCET) of real-time tasks, we should consider various factors (e.g., caching, pipelining, and infeasible paths) that affect the accuracy of the prediction. However some of them are inherently difficult to analyze statically, and thus may give rise to significant overestimation in WCET prediction. Therefore, for more accurate WCET prediction, we need to identify, such overestimation sources and analyze how much each of them can make overestimation. Then, such analysis results can be used to refine existing timing analysis techniques. In this paper we do not propose any new timing analysis techniques, but present quantitative analysis results on the impacts of overestimation sources on the accuracy of the worst case timing analysis. For this purpose, we use variance analysis based on a simulation-based methodology to make our analysis independent of any existing techniques. The results show that the dominant factor is pipelining analysis when the cache miss penalty is small and instruction caching analysis when the cache miss penalty is larger than 10 cycles. The results also show that although the impact of data caching analysis is small compared with that of pipelining or instruction caching analysis, if we ignore its effect in the WCET estimation, the WCET can be overestimated up to 275% even when the effects of the other factors are completely analyzed. Finally, the results show that the effects of infeasible paths are largely orthogonal to other analysis features and depend on program characteristics. Also, as for data caching, if infeasible paths are ignored in the WCET estimation, the accuracy of the WCET estimation is degraded significantly (up to 564%)
Proceedings of the 2007 ACM symposium on Applied computing - SAC '07, 2007
Abstract System software development and testing on embedded systems can be quite difficult and t... more Abstract System software development and testing on embedded systems can be quite difficult and time consuming. In this paper, we propose a cost effective method, namely virtual testing framework that can be used easily to test the reliability of system software. ...
Abstract System software development and testing on embedded systems can be quite difficult and t... more Abstract System software development and testing on embedded systems can be quite difficult and time consuming. In this paper, we propose a cost effective method, namely virtual testing framework that can be used easily to test the reliability of system software. ...
This paper presents a case study of worst case timing analysis for a RISC processor. The target m... more This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine that is built based on the extended timing schema approach. 1 Introduction Calculating tight and safe WCET (Worst Case Execution Time) bounds is an important research topic in the real-time com...
Recent progress in worst case timing analysis of programs has made it possible to perform accurat... more Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessary when a RISC processor is used as the target processor of a real-time system. However, there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer-based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). This paper proposes two techniques to...
Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054), 1999
ABSTRACT To predict the worst case execution time (WCET) of real-time tasks, we should consider v... more ABSTRACT To predict the worst case execution time (WCET) of real-time tasks, we should consider various factors (e.g., caching, pipelining, and infeasible paths) that affect the accuracy of the prediction. However some of them are inherently difficult to analyze statically, and thus may give rise to significant overestimation in WCET prediction. Therefore, for more accurate WCET prediction, we need to identify, such overestimation sources and analyze how much each of them can make overestimation. Then, such analysis results can be used to refine existing timing analysis techniques. In this paper we do not propose any new timing analysis techniques, but present quantitative analysis results on the impacts of overestimation sources on the accuracy of the worst case timing analysis. For this purpose, we use variance analysis based on a simulation-based methodology to make our analysis independent of any existing techniques. The results show that the dominant factor is pipelining analysis when the cache miss penalty is small and instruction caching analysis when the cache miss penalty is larger than 10 cycles. The results also show that although the impact of data caching analysis is small compared with that of pipelining or instruction caching analysis, if we ignore its effect in the WCET estimation, the WCET can be overestimated up to 275% even when the effects of the other factors are completely analyzed. Finally, the results show that the effects of infeasible paths are largely orthogonal to other analysis features and depend on program characteristics. Also, as for data caching, if infeasible paths are ignored in the WCET estimation, the accuracy of the WCET estimation is degraded significantly (up to 564%)
Proceedings of the 2007 ACM symposium on Applied computing - SAC '07, 2007
Abstract System software development and testing on embedded systems can be quite difficult and t... more Abstract System software development and testing on embedded systems can be quite difficult and time consuming. In this paper, we propose a cost effective method, namely virtual testing framework that can be used easily to test the reliability of system software. ...
Abstract System software development and testing on embedded systems can be quite difficult and t... more Abstract System software development and testing on embedded systems can be quite difficult and time consuming. In this paper, we propose a cost effective method, namely virtual testing framework that can be used easily to test the reliability of system software. ...
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Papers by Sung-Kwan Kim