2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008
In modern SOC design, a large number of buffers need to be inserted to a large number of nets to ... more In modern SOC design, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So it is important to avoid over-buffering. Buffering spaces are more limited in the denser regions of a layout. Thus it is also necessary to
ACM Transactions on Design Automation of Electronic Systems, 2008
We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given t... more We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36% lower than those reported in the best previous work in the literature.
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014
ABSTRACT Electron-beam direct write (EBDW) lithography is a promising solution for chip productio... more ABSTRACT Electron-beam direct write (EBDW) lithography is a promising solution for chip production in the sub-22nm regime. To improve the throughput of EBDW lithography, character projection method is commonly employed and a critical problem is to pack as many characters as possible onto the stencil. In this paper, we consider two enhancements in packed stencil design over previous works. First, the use of multiple shaping apertures with different sizes is explored. Second, the fact that the pattern of a character can be located anywhere within its enclosing projection region is exploited to facilitate flexible blank space sharing. For this packed stencil design problem with multiple shaping apertures and flexible blank space sharing, a dynamic programming based algorithm is proposed. Experimental results show that the proposed enhancement and the associated algorithm can significantly reduce the total shot count and hence improve the throughput of EBDW lithography.
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
We present the fastest algorithm known today for computing a global minimum cut in a hypergraph. ... more We present the fastest algorithm known today for computing a global minimum cut in a hypergraph. Unlike most minimum cut algorithms which rely on flow computations in a network, ours is a non-flow based algorithm. Since the netlist of a circuit can be modelled naturally as a hypergraph, this opens the opportunity for finding very high quality solutions for the
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
... De-Yu Liu , Wai-Kei Mak , and Ting-Chi Wang Department of Computer Science, National Tsing Hu... more ... De-Yu Liu , Wai-Kei Mak , and Ting-Chi Wang Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan red921533 ... temperature-aware 3D floorplanners, eg, [4, 5, 6, 7], but they cannot handle the die-stacking SiP floorplan-ning problem because ...
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007
lambda-geometry routing provides more available routing directions on different metal layers for ... more lambda-geometry routing provides more available routing directions on different metal layers for chip interconnection to reduce wirelength. However, it can lead to a significant increase in via cost. In this paper, we consider lambda-geometry zero-skew clock tree construction with wirelength and via minimization. Our lambda-geometry clock router achieves, on average, a 7.57% wirelength reduction in the Y-architecture and 9.68% in the X-architecture when compared with results in the Manhattan architecture. In addition, we also propose a dynamic programming approach to determine the one-bend routes of the clock edges to optimize the total node via cost of the whole clock tree. Our via minimization algorithm can reduce the total via cost by an average of 17% in the Y-architecture and 37% in the X architecture.
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
ABSTRACT Due to process limitations, wiring rules are imposed by foundries on chip layout. Under ... more ABSTRACT Due to process limitations, wiring rules are imposed by foundries on chip layout. Under nanometer wiring rules, the required separation between two wire ends is dependent on their surrounding wires, and there is a limit on the minimum length of each wire segment. Yet, traditional maze routing algorithms are not designed to handle these rules, so rule violations are corrected by post-processing and the quality of result is seriously impacted. For this reason, we propose a new maze routing algorithm capable of handling these wiring rules. The proposed algorithm is proved to find a legal shortest path with time complexity of O(n), where n is the number of grid points. Experiments with seven tight industrial cases show that the runtime of a commercial router is reduced by 2.4 times and the total wire length is also reduced by 3% on average.
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09, 2009
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip... more This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement , only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%.
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008
In modern SOC design, a large number of buffers need to be inserted to a large number of nets to ... more In modern SOC design, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So it is important to avoid over-buffering. Buffering spaces are more limited in the denser regions of a layout. Thus it is also necessary to
ACM Transactions on Design Automation of Electronic Systems, 2008
We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given t... more We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36% lower than those reported in the best previous work in the literature.
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014
ABSTRACT Electron-beam direct write (EBDW) lithography is a promising solution for chip productio... more ABSTRACT Electron-beam direct write (EBDW) lithography is a promising solution for chip production in the sub-22nm regime. To improve the throughput of EBDW lithography, character projection method is commonly employed and a critical problem is to pack as many characters as possible onto the stencil. In this paper, we consider two enhancements in packed stencil design over previous works. First, the use of multiple shaping apertures with different sizes is explored. Second, the fact that the pattern of a character can be located anywhere within its enclosing projection region is exploited to facilitate flexible blank space sharing. For this packed stencil design problem with multiple shaping apertures and flexible blank space sharing, a dynamic programming based algorithm is proposed. Experimental results show that the proposed enhancement and the associated algorithm can significantly reduce the total shot count and hence improve the throughput of EBDW lithography.
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
We present the fastest algorithm known today for computing a global minimum cut in a hypergraph. ... more We present the fastest algorithm known today for computing a global minimum cut in a hypergraph. Unlike most minimum cut algorithms which rely on flow computations in a network, ours is a non-flow based algorithm. Since the netlist of a circuit can be modelled naturally as a hypergraph, this opens the opportunity for finding very high quality solutions for the
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010
... De-Yu Liu , Wai-Kei Mak , and Ting-Chi Wang Department of Computer Science, National Tsing Hu... more ... De-Yu Liu , Wai-Kei Mak , and Ting-Chi Wang Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan red921533 ... temperature-aware 3D floorplanners, eg, [4, 5, 6, 7], but they cannot handle the die-stacking SiP floorplan-ning problem because ...
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007
lambda-geometry routing provides more available routing directions on different metal layers for ... more lambda-geometry routing provides more available routing directions on different metal layers for chip interconnection to reduce wirelength. However, it can lead to a significant increase in via cost. In this paper, we consider lambda-geometry zero-skew clock tree construction with wirelength and via minimization. Our lambda-geometry clock router achieves, on average, a 7.57% wirelength reduction in the Y-architecture and 9.68% in the X-architecture when compared with results in the Manhattan architecture. In addition, we also propose a dynamic programming approach to determine the one-bend routes of the clock edges to optimize the total node via cost of the whole clock tree. Our via minimization algorithm can reduce the total via cost by an average of 17% in the Y-architecture and 37% in the X architecture.
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
ABSTRACT Due to process limitations, wiring rules are imposed by foundries on chip layout. Under ... more ABSTRACT Due to process limitations, wiring rules are imposed by foundries on chip layout. Under nanometer wiring rules, the required separation between two wire ends is dependent on their surrounding wires, and there is a limit on the minimum length of each wire segment. Yet, traditional maze routing algorithms are not designed to handle these rules, so rule violations are corrected by post-processing and the quality of result is seriously impacted. For this reason, we propose a new maze routing algorithm capable of handling these wiring rules. The proposed algorithm is proved to find a legal shortest path with time complexity of O(n), where n is the number of grid points. Experiments with seven tight industrial cases show that the runtime of a commercial router is reduced by 2.4 times and the total wire length is also reduced by 3% on average.
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09, 2009
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip... more This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement , only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%.
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