International Journal of Advanced Computer Science and Applications
This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) a... more This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) architectures: a fast and low Power DCT architecture and a high PSNR DCT architecture. The rotation parameters of CORDIC angles required for these architectures have been calculated using a MATLAB script. This script allows the variation of the angle's precision from 10 −1 to 10 −4. The experimental results show that the fast and low Power DCT architecture correponds to the precision 10 −1. Its complexity is even lower than the BinDCT which is a reference in terms of low complexity and its power has been enhanced in comparison with the conventional Cordic Loeffler DCT by 12 mW. The experimental results also show that the high PSNR DCT architecture corresponds to the precision 10 −3 for which the PSNR has been improved by 6.55 dB in comparison with the conventional Cordic Loeffler DCT. Then, the hardware implementation and the generated RTL of some required Cordics are presented.
International Journal of Advanced Computer Science and Applications
Evaluating embedded systems vulnerability to faults injection attacks has gained importance in re... more Evaluating embedded systems vulnerability to faults injection attacks has gained importance in recent years due to the rising threats they bring to chips security. The task is particularly important for micro-controllers since they have lower resistance to fault attacks compared to hardware-based cryptosystems. This paper reviews recent embedded fault injection simulators from literature and presents an embedded high-level fault injection mechanism based on a Real-Time Operating System (RTOS). The approach aims to be architecture-independent and portable to 32-bit microcontrollers and embedded processors. The proposed mechanism, primarily targets realistic fault attack scenarios on memory locations, is adapted to timed and event-based fault injection. A Differential Fault Attack (DFA) was mounted on a popular ARM-based micro-controller running FreeRTOS to illustrate the proposed mechanism. The aim is also to bridge the embedded fault injection simulation mechanism efficiently to a computerbased cryptanalysis and to highlight the importance of physically protecting the memory and integrating data-specific countermeasures.
The increasing complexity of cryptographic devices requires fast simulation environment in order ... more The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++...
... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, L... more ... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal IBM ... The PSL assertions are embedded in the systemC code as smart comments and are picked up by a perl script from ...
In complex System on Chips (SoCs), system level platforms are built around a set of IPs including... more In complex System on Chips (SoCs), system level platforms are built around a set of IPs including processor cores, memories and dedicated hardware (FPGA, ASIC). The better for modeling is using a single system level language during implementation. However, as IPs are in different languages, there is a need to several adaptations and conversion processes, hence making the platforms un-optimized.
SystemC language as well as the verification library going with (SCV), provides a rich set of fea... more SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at hi... more Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. o modifications are needed in the design's SystemC code. Functional as well as performance properties are addressed. We demonstrate the effectiveness of our approach on TLM 2.0 standard compliant models.
... As manual modeling is error prone and time consuming, in this work, we convert automatically ... more ... As manual modeling is error prone and time consuming, in this work, we convert automatically PSL into cycle accurate assertions coded in SystemC. The assertion alternative, extending SLD flow, does not cover TLM and un-timed designs. They are focus of future works. ...
Transaction level modeling (TLM) has become an accepted and well supported paradigm that is inten... more Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the design's SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.
The authors present a technique to synchronize between PSL (property specification language) chec... more The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that
International Journal of Advanced Computer Science and Applications
This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) a... more This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) architectures: a fast and low Power DCT architecture and a high PSNR DCT architecture. The rotation parameters of CORDIC angles required for these architectures have been calculated using a MATLAB script. This script allows the variation of the angle's precision from 10 −1 to 10 −4. The experimental results show that the fast and low Power DCT architecture correponds to the precision 10 −1. Its complexity is even lower than the BinDCT which is a reference in terms of low complexity and its power has been enhanced in comparison with the conventional Cordic Loeffler DCT by 12 mW. The experimental results also show that the high PSNR DCT architecture corresponds to the precision 10 −3 for which the PSNR has been improved by 6.55 dB in comparison with the conventional Cordic Loeffler DCT. Then, the hardware implementation and the generated RTL of some required Cordics are presented.
International Journal of Advanced Computer Science and Applications
Evaluating embedded systems vulnerability to faults injection attacks has gained importance in re... more Evaluating embedded systems vulnerability to faults injection attacks has gained importance in recent years due to the rising threats they bring to chips security. The task is particularly important for micro-controllers since they have lower resistance to fault attacks compared to hardware-based cryptosystems. This paper reviews recent embedded fault injection simulators from literature and presents an embedded high-level fault injection mechanism based on a Real-Time Operating System (RTOS). The approach aims to be architecture-independent and portable to 32-bit microcontrollers and embedded processors. The proposed mechanism, primarily targets realistic fault attack scenarios on memory locations, is adapted to timed and event-based fault injection. A Differential Fault Attack (DFA) was mounted on a popular ARM-based micro-controller running FreeRTOS to illustrate the proposed mechanism. The aim is also to bridge the embedded fault injection simulation mechanism efficiently to a computerbased cryptanalysis and to highlight the importance of physically protecting the memory and integrating data-specific countermeasures.
The increasing complexity of cryptographic devices requires fast simulation environment in order ... more The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++...
... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, L... more ... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal IBM ... The PSL assertions are embedded in the systemC code as smart comments and are picked up by a perl script from ...
In complex System on Chips (SoCs), system level platforms are built around a set of IPs including... more In complex System on Chips (SoCs), system level platforms are built around a set of IPs including processor cores, memories and dedicated hardware (FPGA, ASIC). The better for modeling is using a single system level language during implementation. However, as IPs are in different languages, there is a need to several adaptations and conversion processes, hence making the platforms un-optimized.
SystemC language as well as the verification library going with (SCV), provides a rich set of fea... more SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at hi... more Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. o modifications are needed in the design's SystemC code. Functional as well as performance properties are addressed. We demonstrate the effectiveness of our approach on TLM 2.0 standard compliant models.
... As manual modeling is error prone and time consuming, in this work, we convert automatically ... more ... As manual modeling is error prone and time consuming, in this work, we convert automatically PSL into cycle accurate assertions coded in SystemC. The assertion alternative, extending SLD flow, does not cover TLM and un-timed designs. They are focus of future works. ...
Transaction level modeling (TLM) has become an accepted and well supported paradigm that is inten... more Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the design's SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.
The authors present a technique to synchronize between PSL (property specification language) chec... more The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that
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Papers by Younes Lahbib