The increasing complexity of cryptographic devices requires fast simulation environment in order ... more The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++...
... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, L... more ... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal IBM ... The PSL assertions are embedded in the systemC code as smart comments and are picked up by a perl script from ...
SystemC language as well as the verification library going with (SCV), provides a rich set of fea... more SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
... As manual modeling is error prone and time consuming, in this work, we convert automatically ... more ... As manual modeling is error prone and time consuming, in this work, we convert automatically PSL into cycle accurate assertions coded in SystemC. The assertion alternative, extending SLD flow, does not cover TLM and un-timed designs. They are focus of future works. ...
Transaction level modeling (TLM) has become an accepted and well supported paradigm that is inten... more Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the design's SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.
The authors present a technique to synchronize between PSL (property specification language) chec... more The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that
The increasing complexity of cryptographic devices requires fast simulation environment in order ... more The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++...
... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, L... more ... Combining System Level Modeling with Assertion Based Verification Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal IBM ... The PSL assertions are embedded in the systemC code as smart comments and are picked up by a perl script from ...
SystemC language as well as the verification library going with (SCV), provides a rich set of fea... more SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
... As manual modeling is error prone and time consuming, in this work, we convert automatically ... more ... As manual modeling is error prone and time consuming, in this work, we convert automatically PSL into cycle accurate assertions coded in SystemC. The assertion alternative, extending SLD flow, does not cover TLM and un-timed designs. They are focus of future works. ...
Transaction level modeling (TLM) has become an accepted and well supported paradigm that is inten... more Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated and generic way. No modifications are needed in the design's SystemC code. In addition, a wide range of functional and performance assertions is addressed. We demonstrate the usefulness of our approach on a realistic system-on-chip platform based on TLM-2.0 standard compliant models and including Open Core Protocol (OCP) interfaces.
The authors present a technique to synchronize between PSL (property specification language) chec... more The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that
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Papers by Younes Lahbib