Pattern Recognition has become an attractive research oriented field of the computer vision and m... more Pattern Recognition has become an attractive research oriented field of the computer vision and machine learning for the last few decades. Neural pattern recognition techniques are also being exercised for pattern recognition, showing promising results. In this paper, a comparison is made between statistical and neural pattern recognition techniques and tried to realize how neural techniques reveal far better results than statistical techniques. In this comparison, Discriminant Analysis (DA) and Principal Component Analysis (PCA) are used for pattern recognition, which are a statistical technique. Discriminant Analysis engrosses the problem of huge data dimensions and small sample size. To evade these problems, pattern recognition task is also implemented using Generalized Regression Neural Network (GRNN) and Back-propagation Neural Network (BPNN) techniques. The task of pattern recognition is conceded on a data base of face images of 400 people. Neural networks proved results for better than statistical methods.
Abstract There is a significant demand for embedding high performance reconfigurable cores within... more Abstract There is a significant demand for embedding high performance reconfigurable cores within future system on chip (SoC) designs as such cores offer flexibility as well as superior performance advantages in terms of speed, power and run time reconfigurability. ...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip ... more In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed up the designer's productivity. This paper aims to produce new high level IP models in SystemC for functional verification of IP integrations, incorporating both embedded custom reconfigurable and conventional IPs, which are optimised in terms of IP Core parameters. As a case study, a novel reconfigurable FFT architecture is presented and modelled in SystemC. Power, area and performance figures are presented as well.
Page 1. Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC B. Ahm... more Page 1. Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC B. Ahmad 1 , Ahmet T. Erdogan 1 , Sami Khawam 1 1: School of Electronics & Engineering University of Edinburgh, King's Buildings ...
This paper describes our communication centric platform based designs for future multi-processor ... more This paper describes our communication centric platform based designs for future multi-processor system-on-chip (MPSoC) architectures. The proposed platforms have built in controller, thus making the heterogeneous IPs (reconfigurable, fixed & processor based) integrated in plug and play fashion. This eliminates the need of dedicated system controller to be integrated or programmed. Three platforms have been developed with different communication medium including a hybrid concept where bus based and crossbar based communication media co-exists in a single SoC. Each pre-verified platform has predicted characteristics and can be selected by user for desired application. The results show comparison of different power, area and throughput characteristics of these platforms.
A new system-level approach is needed to incorporate re-configurability in IP-integration design ... more A new system-level approach is needed to incorporate re-configurability in IP-integration design flow, in order to speed up the designer's productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and co-simulated in a C-based WiMAX system. Area and power consumption of main blocks in WiMAX are analysed.
This paper demonstrates our implementation of a dynamically reconfigurable network on chip router... more This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades. A framework for system level modeling of reconfigurable NoC with reconfigurable components is also proposed and demonstrated in systemC. Results are compared with implementation of the same system with conventional NoC to demonstrate advantages of the proposed NoC architecture.
This paper aims at providing a new system level power estimation methodology based on transaction... more This paper aims at providing a new system level power estimation methodology based on transaction level mod-elling (SystemC) for wireless applications, which can highly improve the trade-off between accuracy and efficiency of power estimation in system level. The main features ...
Pattern Recognition has become an attractive research oriented field of the computer vision and m... more Pattern Recognition has become an attractive research oriented field of the computer vision and machine learning for the last few decades. Neural pattern recognition techniques are also being exercised for pattern recognition, showing promising results. In this paper, a comparison is made between statistical and neural pattern recognition techniques and tried to realize how neural techniques reveal far better results than statistical techniques. In this comparison, Discriminant Analysis (DA) and Principal Component Analysis (PCA) are used for pattern recognition, which are a statistical technique. Discriminant Analysis engrosses the problem of huge data dimensions and small sample size. To evade these problems, pattern recognition task is also implemented using Generalized Regression Neural Network (GRNN) and Back-propagation Neural Network (BPNN) techniques. The task of pattern recognition is conceded on a data base of face images of 400 people. Neural networks proved results for better than statistical methods.
Abstract There is a significant demand for embedding high performance reconfigurable cores within... more Abstract There is a significant demand for embedding high performance reconfigurable cores within future system on chip (SoC) designs as such cores offer flexibility as well as superior performance advantages in terms of speed, power and run time reconfigurability. ...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip ... more In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed up the designer's productivity. This paper aims to produce new high level IP models in SystemC for functional verification of IP integrations, incorporating both embedded custom reconfigurable and conventional IPs, which are optimised in terms of IP Core parameters. As a case study, a novel reconfigurable FFT architecture is presented and modelled in SystemC. Power, area and performance figures are presented as well.
Page 1. Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC B. Ahm... more Page 1. Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC B. Ahmad 1 , Ahmet T. Erdogan 1 , Sami Khawam 1 1: School of Electronics & Engineering University of Edinburgh, King's Buildings ...
This paper describes our communication centric platform based designs for future multi-processor ... more This paper describes our communication centric platform based designs for future multi-processor system-on-chip (MPSoC) architectures. The proposed platforms have built in controller, thus making the heterogeneous IPs (reconfigurable, fixed & processor based) integrated in plug and play fashion. This eliminates the need of dedicated system controller to be integrated or programmed. Three platforms have been developed with different communication medium including a hybrid concept where bus based and crossbar based communication media co-exists in a single SoC. Each pre-verified platform has predicted characteristics and can be selected by user for desired application. The results show comparison of different power, area and throughput characteristics of these platforms.
A new system-level approach is needed to incorporate re-configurability in IP-integration design ... more A new system-level approach is needed to incorporate re-configurability in IP-integration design flow, in order to speed up the designer's productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and co-simulated in a C-based WiMAX system. Area and power consumption of main blocks in WiMAX are analysed.
This paper demonstrates our implementation of a dynamically reconfigurable network on chip router... more This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades. A framework for system level modeling of reconfigurable NoC with reconfigurable components is also proposed and demonstrated in systemC. Results are compared with implementation of the same system with conventional NoC to demonstrate advantages of the proposed NoC architecture.
This paper aims at providing a new system level power estimation methodology based on transaction... more This paper aims at providing a new system level power estimation methodology based on transaction level mod-elling (SystemC) for wireless applications, which can highly improve the trade-off between accuracy and efficiency of power estimation in system level. The main features ...
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