IEEE Transactions on Circuits and Systems I-regular Papers, 2008
A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM i... more A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fmax are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper
This paper presents the design of fully differential second-order delta-sigma modulator. A curren... more This paper presents the design of fully differential second-order delta-sigma modulator. A current feedback technique is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance and to improve the transmission error in the memory cell. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. In this paper, the SDM is simulated with TSMC 0.35 micrometre CMOS process technology. The simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 75 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 16 mW.
... Shuenn-Yuh Lee Department of Electrical Engineering National Chung-Cheng University 160, San-... more ... Shuenn-Yuh Lee Department of Electrical Engineering National Chung-Cheng University 160, San-Hsing Ming-Hsiung Phone:+886-5-2720411-33223, Fax:+886-5-2720862 ABSTRACT This paper is an aim on the representation of a second-order Sigma-Delta Modulator (SDM ...
Smart sensors play a critical role in modern automotive electronic systems, covering a wide range... more Smart sensors play a critical role in modern automotive electronic systems, covering a wide range of data capturing functions and operating under adverse environmental conditions - temperature range of [-40ºC,175ºC]. In such sensors, the signal provided by transducers is composed of an offset voltage, which depends on the manufacturing process, and a low-frequency signal carrying the information. In practice, the offset voltage is subject to temperature variations, thus causing a shifting of the signal range to be measured. Therefore, the measuring circuit driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC), must accommodate the complete range of possible offsets and real signals. In this scenario, the use of ADCs based on Sigma-Delta Modulators (SDMs) is convenient for several reasons. On the one hand, the noise-shaping performed by SDMs allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of SDMs with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation. This feature allows to accommodate the complete range of possible offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes the design and implementation of a third-order cascade (2-1) SDM with programmable gain in a 0.35mm CMOS technology - the type of technology commonly employed for automotive applications (deep submicron is mostly employed for telecom). It is capable of handling signals up to 20-kHz bandwidth with 17-bit resolution. The programmable gain is implemented by a capacitor array whose unitary capacitors are connected or disconnected depending on the value of the selected gain. In order to relax the amplifier dynamics requirements as the modulator gain varies, switchable capacitor arrays have been used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. As a result, a dynamic range equal to 105 dB is obtained for all cases of the modulator gain, which corresponds to 17 bit resolution.
A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complex... more A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complexity is proposed in this paper. The purpose of the detection is reducing complexity from sphere decoder and having better performance than successive cancellation detection with QR decomposition (QR-SCD) and vertical Bell laboratories layered space-time (V-BLAST). In a perfect channel estimated receiver, the simulation of JQRPSD method performs the performance approaching the performance of sphere decoder algorithm. The proposed detector is designed by TSMC 0.18 mum CMOS technology without preprocessor in 4 x 4 multiple input and multiple output (MIMO) wireless communication.
An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a... more An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a 10-bit dynamic range for bio-microsystem applications is presented. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the over-sampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class AB memory cell are low-power consumption, high linearity, and high dynamic range. For the various applications with different biosignal frequencies, the SISDM could be operated in different operation mode. The overall SDM with core area of 0.05mm2 has been implemented in a TSMC 0.18mum 1P6M standard CMOS process technology. Without voltage booster to raise the gate voltage of switches, post-layout simulation results show that the SISDM has a dynamic range over 60dB and a power consumption of 180muW with an input signal of 1.25kHz sinusoid wave and 5kHz bandwidth under a single 0.8V power supply for ENG signals
IEEE Transactions on Circuits and Systems I-regular Papers, 2008
A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM i... more A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fmax are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper
This paper presents the design of fully differential second-order delta-sigma modulator. A curren... more This paper presents the design of fully differential second-order delta-sigma modulator. A current feedback technique is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance and to improve the transmission error in the memory cell. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. In this paper, the SDM is simulated with TSMC 0.35 micrometre CMOS process technology. The simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 75 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 16 mW.
... Shuenn-Yuh Lee Department of Electrical Engineering National Chung-Cheng University 160, San-... more ... Shuenn-Yuh Lee Department of Electrical Engineering National Chung-Cheng University 160, San-Hsing Ming-Hsiung Phone:+886-5-2720411-33223, Fax:+886-5-2720862 ABSTRACT This paper is an aim on the representation of a second-order Sigma-Delta Modulator (SDM ...
Smart sensors play a critical role in modern automotive electronic systems, covering a wide range... more Smart sensors play a critical role in modern automotive electronic systems, covering a wide range of data capturing functions and operating under adverse environmental conditions - temperature range of [-40ºC,175ºC]. In such sensors, the signal provided by transducers is composed of an offset voltage, which depends on the manufacturing process, and a low-frequency signal carrying the information. In practice, the offset voltage is subject to temperature variations, thus causing a shifting of the signal range to be measured. Therefore, the measuring circuit driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC), must accommodate the complete range of possible offsets and real signals. In this scenario, the use of ADCs based on Sigma-Delta Modulators (SDMs) is convenient for several reasons. On the one hand, the noise-shaping performed by SDMs allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of SDMs with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation. This feature allows to accommodate the complete range of possible offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes the design and implementation of a third-order cascade (2-1) SDM with programmable gain in a 0.35mm CMOS technology - the type of technology commonly employed for automotive applications (deep submicron is mostly employed for telecom). It is capable of handling signals up to 20-kHz bandwidth with 17-bit resolution. The programmable gain is implemented by a capacitor array whose unitary capacitors are connected or disconnected depending on the value of the selected gain. In order to relax the amplifier dynamics requirements as the modulator gain varies, switchable capacitor arrays have been used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. As a result, a dynamic range equal to 105 dB is obtained for all cases of the modulator gain, which corresponds to 17 bit resolution.
A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complex... more A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complexity is proposed in this paper. The purpose of the detection is reducing complexity from sphere decoder and having better performance than successive cancellation detection with QR decomposition (QR-SCD) and vertical Bell laboratories layered space-time (V-BLAST). In a perfect channel estimated receiver, the simulation of JQRPSD method performs the performance approaching the performance of sphere decoder algorithm. The proposed detector is designed by TSMC 0.18 mum CMOS technology without preprocessor in 4 x 4 multiple input and multiple output (MIMO) wireless communication.
An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a... more An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a 10-bit dynamic range for bio-microsystem applications is presented. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the over-sampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class AB memory cell are low-power consumption, high linearity, and high dynamic range. For the various applications with different biosignal frequencies, the SISDM could be operated in different operation mode. The overall SDM with core area of 0.05mm2 has been implemented in a TSMC 0.18mum 1P6M standard CMOS process technology. Without voltage booster to raise the gate voltage of switches, post-layout simulation results show that the SISDM has a dynamic range over 60dB and a power consumption of 180muW with an input signal of 1.25kHz sinusoid wave and 5kHz bandwidth under a single 0.8V power supply for ENG signals
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