Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521), 2004
In this paper a pure digital CMOS (90nm) dual band GSM low IF (1OOkHz) receiver section is presen... more In this paper a pure digital CMOS (90nm) dual band GSM low IF (1OOkHz) receiver section is presented. The incoming RF signal is first amplified using two differential LNAs (one for GSM and the other for DCS) and then down converted by two passive mixers to produce the low frequency I and Q signals. The 90 degrees phase shifted local oscillator signals are implemented on chip using two dividers by 4 and by 2 (working at 3.6GHz). The low IF strip will amplify and filter the I and Q signals. It has been built with digitally programmable gain stages including also a Buttemorth 2"d order polyphase active filter. The receiver has been designed to be compatible with a standard 10-bits ADC. The RX chain shows state-of-the-art NF performances (<2dB in GSM and <3dB in DCS) with an overall current consumption of 29mA at 1.4V supply (9mA for the.LNA, 17mA for the IF strip and 3mA for the divider by 2). The die area is 1.4mmx2.8mm. I.
Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521), 2004
The programmable analog Power Amplifier (PA) control loop of a fully-integrated GSM/GPRS quad-ban... more The programmable analog Power Amplifier (PA) control loop of a fully-integrated GSM/GPRS quad-band transceiver [1][2] is presented. The control loop is based on a fully-integrated PA controller which meets all ETSI GSMlGPRS requirements. Both the gain and the bandwidth of the PA control loop are programmable as well as the stand-by voltage delivered to the PA. These features, together with a high driving capability (8.4mA @ 2.5V), make this solution capable to interface vast combinations of PAS, couplers and detectors. The proposed PA controller has been integrated in a BiCMOS SiGe 0.35pm process and measures 0.33mm2. The current consumption from a single 2.8V power supply is 2.8mA without load and 7.2rnA in the application (using Hitachi's PF08109B PA).
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003
A fully integrated 2 A fractional Synthesizer (included VCO, Loop Filter, Xtal oscillator negativ... more A fully integrated 2 A fractional Synthesizer (included VCO, Loop Filter, Xtal oscillator negative impedance) is implemented in a 0.4 um, 45 GHz (SiGe) BiCMOS. The measured close in phase noise is-106 dBdHz at 900 MHz using 26 MHz comparison frequency and frequency resolution less than 5Hz is achieved. The VCO's inductors are not integrated in order to test the PLL performance on different frequency's range. Using a 200 KHz close loop bandwidth the level of the tones generated, when critical channels are synthesized, exceed the GSM transmitter specifications without applying any dithering technique. The very low close in phase noise and low level of tone generation, make it suitable for "indirect GMSK VCO modulation" application
3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel sta... more 3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and
We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the cr... more We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the crystal oscillator) suitable for GPRS kind of application. The complete solution with the VCO integrated has been tested in the range (3 GHz to 3.7GHz) and also measurements @ 900MHz are presented using an external VCO. The chip has been processed in TI BiCMOS SiGe technology (45GHz ft) with 5 level of metal (the fifth metal in cupper). The complete PLL is 1.2mm 2 (fig.I.I) including the integrated and programmable filter and the integrated VCO. The overall current consumption is 15mA @ 2.7V supply (6mA for the PLL and 9mA for the VCO). The close in noise performances are the state of the art of the integrated pll -96.5dBc/Hz @ 1KHz offset with fout=900 MHz (external VCO) and fref=400KHz. The frequency range of the PLL (excluding the VCO) is up to 4.2 GHz. The settling time within 1KHz is <85us at fout=3.52GHz with -75dBc spurious @ 400KHz offset and -85dBc spurious @ 800KHz offset.
Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur pa... more Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur par prise d'un signal directement de l'element resonant, tel qu'un cristal, d'un oscillateur dans le premier recepteur afin d'exciter l'entree du deuxieme recepteur. Le signal sinusoidal provenant de l'element resonant est relativement exempt d'harmoniques et minimise les interferences pouvant etre induites par les harmoniques d'un couplage de signal d'onde carree ou d'un signal amplifie. L'oscillateur de chaque recepteur peut etre active ou desactive selectivement afin de permettre au recepteur de generer ou recevoir la reference de frequence. Cette technique de couplage peut etre utilisee pour le couplage d'un signal de reference de frequence entre des recepteurs de circuit integre.
Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF... more Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF functions. This fully integrated direct conversion transceiver for GPRS GSM/DCS/PCS applications respond to all above-mentioned criteria. The chip is fulfilling the GPRS specs (settling time < 145us) with a very low overall RX NF (2.8/3.6/3.9 dB for GSM/DCS/PCS), a very good overall TX phase error (2.1/2.3 deg rms for GSM/DCS) and a low DC offset (+/-150mV). This device is realized using BiCMOS 0.35u technology.
Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521), 2004
In this paper a pure digital CMOS (90nm) dual band GSM low IF (1OOkHz) receiver section is presen... more In this paper a pure digital CMOS (90nm) dual band GSM low IF (1OOkHz) receiver section is presented. The incoming RF signal is first amplified using two differential LNAs (one for GSM and the other for DCS) and then down converted by two passive mixers to produce the low frequency I and Q signals. The 90 degrees phase shifted local oscillator signals are implemented on chip using two dividers by 4 and by 2 (working at 3.6GHz). The low IF strip will amplify and filter the I and Q signals. It has been built with digitally programmable gain stages including also a Buttemorth 2"d order polyphase active filter. The receiver has been designed to be compatible with a standard 10-bits ADC. The RX chain shows state-of-the-art NF performances (<2dB in GSM and <3dB in DCS) with an overall current consumption of 29mA at 1.4V supply (9mA for the.LNA, 17mA for the IF strip and 3mA for the divider by 2). The die area is 1.4mmx2.8mm. I.
Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521), 2004
The programmable analog Power Amplifier (PA) control loop of a fully-integrated GSM/GPRS quad-ban... more The programmable analog Power Amplifier (PA) control loop of a fully-integrated GSM/GPRS quad-band transceiver [1][2] is presented. The control loop is based on a fully-integrated PA controller which meets all ETSI GSMlGPRS requirements. Both the gain and the bandwidth of the PA control loop are programmable as well as the stand-by voltage delivered to the PA. These features, together with a high driving capability (8.4mA @ 2.5V), make this solution capable to interface vast combinations of PAS, couplers and detectors. The proposed PA controller has been integrated in a BiCMOS SiGe 0.35pm process and measures 0.33mm2. The current consumption from a single 2.8V power supply is 2.8mA without load and 7.2rnA in the application (using Hitachi's PF08109B PA).
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003
A fully integrated 2 A fractional Synthesizer (included VCO, Loop Filter, Xtal oscillator negativ... more A fully integrated 2 A fractional Synthesizer (included VCO, Loop Filter, Xtal oscillator negative impedance) is implemented in a 0.4 um, 45 GHz (SiGe) BiCMOS. The measured close in phase noise is-106 dBdHz at 900 MHz using 26 MHz comparison frequency and frequency resolution less than 5Hz is achieved. The VCO's inductors are not integrated in order to test the PLL performance on different frequency's range. Using a 200 KHz close loop bandwidth the level of the tones generated, when critical channels are synthesized, exceed the GSM transmitter specifications without applying any dithering technique. The very low close in phase noise and low level of tone generation, make it suitable for "indirect GMSK VCO modulation" application
3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel sta... more 3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and
We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the cr... more We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the crystal oscillator) suitable for GPRS kind of application. The complete solution with the VCO integrated has been tested in the range (3 GHz to 3.7GHz) and also measurements @ 900MHz are presented using an external VCO. The chip has been processed in TI BiCMOS SiGe technology (45GHz ft) with 5 level of metal (the fifth metal in cupper). The complete PLL is 1.2mm 2 (fig.I.I) including the integrated and programmable filter and the integrated VCO. The overall current consumption is 15mA @ 2.7V supply (6mA for the PLL and 9mA for the VCO). The close in noise performances are the state of the art of the integrated pll -96.5dBc/Hz @ 1KHz offset with fout=900 MHz (external VCO) and fref=400KHz. The frequency range of the PLL (excluding the VCO) is up to 4.2 GHz. The settling time within 1KHz is <85us at fout=3.52GHz with -75dBc spurious @ 400KHz offset and -85dBc spurious @ 800KHz offset.
Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur pa... more Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur par prise d'un signal directement de l'element resonant, tel qu'un cristal, d'un oscillateur dans le premier recepteur afin d'exciter l'entree du deuxieme recepteur. Le signal sinusoidal provenant de l'element resonant est relativement exempt d'harmoniques et minimise les interferences pouvant etre induites par les harmoniques d'un couplage de signal d'onde carree ou d'un signal amplifie. L'oscillateur de chaque recepteur peut etre active ou desactive selectivement afin de permettre au recepteur de generer ou recevoir la reference de frequence. Cette technique de couplage peut etre utilisee pour le couplage d'un signal de reference de frequence entre des recepteurs de circuit integre.
Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF... more Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF functions. This fully integrated direct conversion transceiver for GPRS GSM/DCS/PCS applications respond to all above-mentioned criteria. The chip is fulfilling the GPRS specs (settling time < 145us) with a very low overall RX NF (2.8/3.6/3.9 dB for GSM/DCS/PCS), a very good overall TX phase error (2.1/2.3 deg rms for GSM/DCS) and a low DC offset (+/-150mV). This device is realized using BiCMOS 0.35u technology.
Uploads
Papers by stefano cipriani