3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel sta... more 3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and
We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the cr... more We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the crystal oscillator) suitable for GPRS kind of application. The complete solution with the VCO integrated has been tested in the range (3 GHz to 3.7GHz) and also measurements @ 900MHz are presented using an external VCO. The chip has been processed in TI BiCMOS SiGe technology (45GHz ft) with 5 level of metal (the fifth metal in cupper). The complete PLL is 1.2mm 2 (fig.I.I) including the integrated and programmable filter and the integrated VCO. The overall current consumption is 15mA @ 2.7V supply (6mA for the PLL and 9mA for the VCO). The close in noise performances are the state of the art of the integrated pll -96.5dBc/Hz @ 1KHz offset with fout=900 MHz (external VCO) and fref=400KHz. The frequency range of the PLL (excluding the VCO) is up to 4.2 GHz. The settling time within 1KHz is <85us at fout=3.52GHz with -75dBc spurious @ 400KHz offset and -85dBc spurious @ 800KHz offset.
Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur pa... more Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur par prise d'un signal directement de l'element resonant, tel qu'un cristal, d'un oscillateur dans le premier recepteur afin d'exciter l'entree du deuxieme recepteur. Le signal sinusoidal provenant de l'element resonant est relativement exempt d'harmoniques et minimise les interferences pouvant etre induites par les harmoniques d'un couplage de signal d'onde carree ou d'un signal amplifie. L'oscillateur de chaque recepteur peut etre active ou desactive selectivement afin de permettre au recepteur de generer ou recevoir la reference de frequence. Cette technique de couplage peut etre utilisee pour le couplage d'un signal de reference de frequence entre des recepteurs de circuit integre.
Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF... more Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF functions. This fully integrated direct conversion transceiver for GPRS GSM/DCS/PCS applications respond to all above-mentioned criteria. The chip is fulfilling the GPRS specs (settling time < 145us) with a very low overall RX NF (2.8/3.6/3.9 dB for GSM/DCS/PCS), a very good overall TX phase error (2.1/2.3 deg rms for GSM/DCS) and a low DC offset (+/-150mV). This device is realized using BiCMOS 0.35u technology.
3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel sta... more 3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and
We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the cr... more We present in this paper a fully integrated integer PLL synthesizer (including the VCO and the crystal oscillator) suitable for GPRS kind of application. The complete solution with the VCO integrated has been tested in the range (3 GHz to 3.7GHz) and also measurements @ 900MHz are presented using an external VCO. The chip has been processed in TI BiCMOS SiGe technology (45GHz ft) with 5 level of metal (the fifth metal in cupper). The complete PLL is 1.2mm 2 (fig.I.I) including the integrated and programmable filter and the integrated VCO. The overall current consumption is 15mA @ 2.7V supply (6mA for the PLL and 9mA for the VCO). The close in noise performances are the state of the art of the integrated pll -96.5dBc/Hz @ 1KHz offset with fout=900 MHz (external VCO) and fref=400KHz. The frequency range of the PLL (excluding the VCO) is up to 4.2 GHz. The settling time within 1KHz is <85us at fout=3.52GHz with -75dBc spurious @ 400KHz offset and -85dBc spurious @ 800KHz offset.
Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur pa... more Une premiere reference de frequence de recepteur est couplee passivement a un second recepteur par prise d'un signal directement de l'element resonant, tel qu'un cristal, d'un oscillateur dans le premier recepteur afin d'exciter l'entree du deuxieme recepteur. Le signal sinusoidal provenant de l'element resonant est relativement exempt d'harmoniques et minimise les interferences pouvant etre induites par les harmoniques d'un couplage de signal d'onde carree ou d'un signal amplifie. L'oscillateur de chaque recepteur peut etre active ou desactive selectivement afin de permettre au recepteur de generer ou recevoir la reference de frequence. Cette technique de couplage peut etre utilisee pour le couplage d'un signal de reference de frequence entre des recepteurs de circuit integre.
Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF... more Mobile phones demand for smaller more integrated and cost effective solutions to implement the RF functions. This fully integrated direct conversion transceiver for GPRS GSM/DCS/PCS applications respond to all above-mentioned criteria. The chip is fulfilling the GPRS specs (settling time < 145us) with a very low overall RX NF (2.8/3.6/3.9 dB for GSM/DCS/PCS), a very good overall TX phase error (2.1/2.3 deg rms for GSM/DCS) and a low DC offset (+/-150mV). This device is realized using BiCMOS 0.35u technology.
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Papers by stefano cipriani