2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021
Onboard digital processors are the emerging technological developments in the arena of satellite ... more Onboard digital processors are the emerging technological developments in the arena of satellite communication for its on-board flexibility, configurability and programmability. SSPAs (Solid State Power amplifiers) are common components in the RF chain of payloads. It can be sourced by multi carriers and can be driven into saturation by any of the individual carriers. Therefore, power limiter is required per channel for controlling the input power to SSPA from digital processor. Since the processor comprise of digital subsystems the work aims at a FPGA based design and development of feed-forward configurable power limiter having 30dB dynamic range. The architecture comprises of power detector, real time input maximum detector and input signal normalizing modules. It has two modes of operation: linear power mode and limiting power mode. It can be configured with thresholds from 0 dB to -5dB in steps of 0.5dB.
2015 19th International Symposium on VLSI Design and Test, 2015
There are two main directions in the development of modern microprocessor architectures used for ... more There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions per cycle with only one third area increase. Application to perform FFT/IFFT is developed and tested using enhanced architecture of LEON3 IP core for superscalar processing. Performance enhancement of LEON3 core is also compared with Very Long Instruction Word (VLIW) processor and Silicon labs application note. The enhanced SoC is synthesized and implemented on Actel FPGA ProASIC3E. The area, power and timing comparison is shown. Approximately 33% enhancement in execution time is obtained due to the proposed super scaling scheme for LEON3 IP core.
2015 19th International Symposium on VLSI Design and Test, 2015
Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduce... more Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduced as a successor for the DVB-S system. This standard is compatible with multiple input protocols (IP, MPEG-2, MPEG-4) which are either encapsulated in transport stream or generic stream. This encapsulation feature makes it possible to support voice, video as well as data known as the triple play. This protocol is also an open standard, which leads to interoperability among different service providers. This protocol is highly suitable for on-board processing satellite as different class of users can be serviced through a single system as well as low cost ground receiver are available. The design described here implements DVB-S2 frame structure for transport stream, single input with constant code rate of 1/2 and QPSK modulation, with a roll-off of 0.20. A Xilinx Virtex®-5 FPGA is used to implement this design as this FPGA is also available in radiation tolerant version.
Interoperability and compatibility is the main goal for current GNSS systems. A concept of Global... more Interoperability and compatibility is the main goal for current GNSS systems. A concept of Global Navigation Satellite System (GNSS) is to use all navigation system together to provide better capabilities compared with those that would be achieved relying solely on one service or signal. Compatibility, on the other hand, assures that existing GNSS signal is not degrading each other below certain threshold. GNSS provider is concerned about their own signal as well as other signals from different service provider for co-existence. For this reason interference analysis of current GNSS signal is the most needed requirement in current scenario. India is developing its own regional navigation systems named as Indian Regional Navigation Satellite System (IRNSS).An in-house tool is developed with suitable Graphic User Interface (GUI) which provides static analysis of different type of interference parameters and indicates its compatibility with already existing signals. Using the tool, this...
Precise determination of the metallic rubidium (Rb) inside a Rb bulb is critical to the life of o... more Precise determination of the metallic rubidium (Rb) inside a Rb bulb is critical to the life of on-board RAFS. Calorimetric mass estimation is an accurate and non-destructive method to validate the Rb content, without deforming the glass bulb under test. We present a faithful and precise calorimetric method using an indigenous cold-point-formation apparatus (CPA), which efficiently collects the metallic Rb in the glass bulb for a precise calorimetric estimation (±20μg\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\pm 20 \mu g$$\end{document}). We have also performed repeated mass estimations with our calorimetric method revealing a maximum estimation difference only of about 10μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$10\,\mu$$\end{document}g. Further, with the ongoing life test of five Rb bulbs, we report a preliminary estimate of Rb consumption rate inside our bulbs as 0.64 μg/hr\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu g/\sqrt{h}r$$\end{document}, which is in good agreement with the previously reported results.
NavIC (Navigation with Indian Constellation) is a regional satellite navigation system called Ind... more NavIC (Navigation with Indian Constellation) is a regional satellite navigation system called Indian Regional Navigation Satellite System (IRNSS). The NavIC is presently composed of seven operational satellite configuration geometry. We present indigenously designed and developed RAFS for NavIC, named IRAFS—Indian Rubidium Atomic Frequency Standard. The IRAFS Physics Package (PP) and electronics have novel design features, as explained in this article. We present the IRAFS performances tested in thermo-vacuum conditions demonstrating < 2 × 10–12τ−1/2 stability, reaching a flicker floor of 3 × 10–14 with a drift of < 5 × 10–13/day. The IRAFS has a mass of 7.6 kg, a volume of 16 L, and consumes power of 75 W at warm-up and < 40 W in normal operation.
Advanced satellite communication systems should be capable of preventing unauthorized access or e... more Advanced satellite communication systems should be capable of preventing unauthorized access or exploitation of communication services by adversaries. This can be achieved by use of wideband multi-channel digital transceivers which employ channelizer to extract the channel of interest from digitized RF bands for further baseband processing. Various anti-jamming techniques like Frequency hopping are used to prevent the systems from intentional jamming by the hostile systems. This paper presents an efficient channelizer architecture which supports wideband as well as narrowband channels with programmable channel bandwidth followed by frequency hopping for the proposed SATCOM system. The target design is a flexible channelization unit which divides the incoming data links of 11 MHz bandwidth into two data links in granularity of 0.5 MHz depending upon user requirements. First link is further sub-channelized into two sub-links each having a bandwidth of 25 KHz that is frequency hopped a...
Noise estimation of atomic clock is one of the important research areas in the field of atomic cl... more Noise estimation of atomic clock is one of the important research areas in the field of atomic clock development and application. Most of the atomic clocks are having random-stochastic noises and periodic noises due to temperature variation. Random-stochastic noises have a well identified signature in time domain but periodic noises are difficult to analyze in time domain. However, in this paper, an effort is made to identify and analyze the deterministic trends of both random-stochastic noises and periodic noises due to variation in temperature using an alternate approach of least-squares normalized-error (LSNE) regression algorithm. A MATLAB based application with graphical user interface (GUI) is developed to estimate and analyze random-stochastic noises and periodic noises and re-estimate the stability of rubidium atomic clock after removing these noises from the raw phase data. The estimation of stationary noises are done using Allan variance from time domain data and noise pro...
2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), 2016
This paper describes the design and in-house development of FPGA based Digital Beam Forming Hardw... more This paper describes the design and in-house development of FPGA based Digital Beam Forming Hardware for 16 elements configuration. Key function of the System involves electronic steering of beam in desired direction to provide anti-jamming feature in communication and navigation satellites. This system has capability to maximize the received power in the direction of signal of interest & minimize the power in the direction of interference. Digital down conversion (DDC) technique is incorporated in the design for providing flexible channel architectures. Dynamic phase calibration and weight uploading facility is included to provide beam forming capability in real time without any hardware penalty.
This paper presents the design and implementation of an effective Single Event Upset (SEU) mitiga... more This paper presents the design and implementation of an effective Single Event Upset (SEU) mitigation technique for radtolerant Xilinx virtex-4xqr4vsx55FPGA used in Digital Bandwidth Efficient Filter (DBEF) subsystem for a Geostationary mission. The Single Event Effects (SEE) on the virtex-4FPGA are minimized using an external scrubbing engine, which is implemented using rad-hard RTSX32SU-CQ84 Actel FPGA. The availability and reliability analysis shows an optimum window for performing scrubbing function in Geo-stationary earth orbit.
2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016
An open standard compatible onboard processing system is under development, which provides mesh c... more An open standard compatible onboard processing system is under development, which provides mesh connectivity between different user terminals. The system is designed to be compatible to Digital Video Broadcasting - Return Channel via Satellite (DVB-RCS) protocol in uplink and Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) in downlink channels. Due to widespread use of this protocol in DTH, low cost compatible terminals are widely available in market. The main elements of this system are DVB-RCS burst demodulator and decoder, protocol convertor, baseband processor with channel estimator and DVB-S2 modulator. This work presents the architecture of baseband processing and channel estimation module. So this requires advanced micro-controller and fast digital signal processor. Also this processor can be time shared for timing recovery module of burst demodulator. Since the system is designed to be implemented as an onboard processor (OBP) for communication satellite, therefore LEON-3 processor and Digital Signal Processor (DSP) SMJ320C6701 are chosen due to availability of their radiation tolerant versions. This paper presents an interface between LEON-3 and DSP for faster execution of both base band processing and floating point operations. Simulation of interface is done on ModelSim® and performance evaluation and comparison has been done on simulators. TSIM2 simulator is used to simulate LEON-3 where as to simulate DSP SMJ320C6701, Code Composer Studio v5 is used.
The communication links at high speed requires bit synchronizer for countering bit phase misalign... more The communication links at high speed requires bit synchronizer for countering bit phase misalignment at the receive end. This paper describes the design of IC based digital bit synchronizer for high speed optical communication links. It supports data rate from 10 Mbps to1 Gbps. The design shows the excellent jitter and eye performance with an eye opening of 95.5% at data rate of 1Gbps. The test results shows that worst case total root mean square jitter is 28.6 picoseconds exceeding the nominal standards of SONET jitter requirements.
2013 Third International Conference on Advances in Computing and Communications, 2013
In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports va... more In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports variable data rates varying from 4.88Kbps to 2Mbps and higher is described. The paper presents the design of carrier and symbol recovery loops in details. The design is made platform independent so that it can be ported to any FPGA device. Proposed design is targeted for Xilinx Virtex-II pro FPGA xc2vp50-6ff 1152 for Hardware proof of concept. The complete demodulator occupies only 13% of the available logic slices in Xilinx Virtex-II pro FPGA device.
2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems, 2009
The Base Band Processor and Switching System is one of the important Subsystem of GSAT-4 satellit... more The Base Band Processor and Switching System is one of the important Subsystem of GSAT-4 satellite. This paper discusses unique approach to handle multiple interrupts on system having constraint on limited external interrupts of micro-controller. The system also has to be optimized with limited resources available on board in terms of memory, power consumption and speed. This is an embedded system with program development in assembly language with careful selection of hardware and software partition of system. GSAT-4 Ka band payload with Regenerative transponder is a unique mission in the history of Indian Space Program. This Regenerative payload will lead ISRO into a new era of Advanced Communication Satellite Systems.
2014 International Conference on Signal Processing and Integrated Networks (SPIN), 2014
Automatic identification of the digital modulation type of asignal has found applications in many... more Automatic identification of the digital modulation type of asignal has found applications in many areas, including software defined radio (SDR), surveillance and threat analysis. This paper describes the FPGA based implementation of Automatic Modulation Recognition (AMR) algorithm foradvanced communication payload. A wavelet transform based algorithm which involves multi-rate signal processing, is realizedto distinguish QAM, PSK and FSK digital modulation signal in noisy environment. The approach is to use wavelet transform to extract the transient characteristics ina digital modulation signal to identify the type of modulation. The optimum thresholds are derivedfrom rigorous simulation in MATLAB/Simulinkunder the condition that the input noise is Additive WhiteGaussian (AWGN). The performance of the identification schemeis investigated through simulations. The design is implemented and tested in Xilinx Virtex-4 FPGA based card.
In satellite communication deep space mission are the most challenging mission, where system has ... more In satellite communication deep space mission are the most challenging mission, where system has to work at very low Eb/No. Concatenated codes are the ideal choice for such deep space mission. ISRO is planning to send unmanned mission for Mars and several deep space missions in future to study and detailed understanding of our own universe. This paper basically reviews the concatenated convolutional code structure and selects the suitable candidate for our future deep space mission. The complete simulation using Simulink is done and results are presented in this paper.
2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), 2019
This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC... more This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC) encoder for DVB S2 system which includes BCH code followed by LDPC code and finally bit mapped to constellation for QPSK modulation. DVB-S2 FEC: ($\mathbf{n}=64800,\ \mathbf{k}=32400$) rate 1/2 code, with QPSK modulation scheme is considered as target for FPGA implementation. The architecture in this design efficiently uses pipeline technique along with parallel processing to optimize the hardware resources and overall latency, to accomplish FEC encoding for DVB S2 system. Coding is completed in Verilog HDL with Xilinx Virtex6 XC6VLX240T FPGA as target for hardware realization and QuestaSim simulator is used to complete the functional simulation.
In many low-noise applications, extracting information from the extremely noisy signal is require... more In many low-noise applications, extracting information from the extremely noisy signal is required. This task can be accomplished by a lock-in amplifier if the frequency of the signal is known before detection. Error signal output from the physics package of the rubidium atomic clock (RbAC) is one of those noisy signals. A lock-in amplifier extracts the desired information from such a signal as the frequency of the error signal is known beforehand. The Space Applications Centre of the Indian Space Research Organisation is developing the Indian Rubidium Atomic Frequency Standard (IRAFS) for Navigation with Indian Constellation. We have developed a digital lock-in amplifier with a very high-resolution frequency control voltage for IRAFS. This paper demonstrates the digital lock-in amplifier with a novel method of combining two 12-bit digital-to-analog converters (DACs) to get higher resolution 20-bit output for precise frequency control and tuning. This design technique allows a digital lock-in amplifier to be used for high-performance RbAC for space applications as precision DACs with higher resolution are not available in space-qualified versions.
2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021
Onboard digital processors are the emerging technological developments in the arena of satellite ... more Onboard digital processors are the emerging technological developments in the arena of satellite communication for its on-board flexibility, configurability and programmability. SSPAs (Solid State Power amplifiers) are common components in the RF chain of payloads. It can be sourced by multi carriers and can be driven into saturation by any of the individual carriers. Therefore, power limiter is required per channel for controlling the input power to SSPA from digital processor. Since the processor comprise of digital subsystems the work aims at a FPGA based design and development of feed-forward configurable power limiter having 30dB dynamic range. The architecture comprises of power detector, real time input maximum detector and input signal normalizing modules. It has two modes of operation: linear power mode and limiting power mode. It can be configured with thresholds from 0 dB to -5dB in steps of 0.5dB.
2015 19th International Symposium on VLSI Design and Test, 2015
There are two main directions in the development of modern microprocessor architectures used for ... more There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions per cycle with only one third area increase. Application to perform FFT/IFFT is developed and tested using enhanced architecture of LEON3 IP core for superscalar processing. Performance enhancement of LEON3 core is also compared with Very Long Instruction Word (VLIW) processor and Silicon labs application note. The enhanced SoC is synthesized and implemented on Actel FPGA ProASIC3E. The area, power and timing comparison is shown. Approximately 33% enhancement in execution time is obtained due to the proposed super scaling scheme for LEON3 IP core.
2015 19th International Symposium on VLSI Design and Test, 2015
Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduce... more Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduced as a successor for the DVB-S system. This standard is compatible with multiple input protocols (IP, MPEG-2, MPEG-4) which are either encapsulated in transport stream or generic stream. This encapsulation feature makes it possible to support voice, video as well as data known as the triple play. This protocol is also an open standard, which leads to interoperability among different service providers. This protocol is highly suitable for on-board processing satellite as different class of users can be serviced through a single system as well as low cost ground receiver are available. The design described here implements DVB-S2 frame structure for transport stream, single input with constant code rate of 1/2 and QPSK modulation, with a roll-off of 0.20. A Xilinx Virtex®-5 FPGA is used to implement this design as this FPGA is also available in radiation tolerant version.
Interoperability and compatibility is the main goal for current GNSS systems. A concept of Global... more Interoperability and compatibility is the main goal for current GNSS systems. A concept of Global Navigation Satellite System (GNSS) is to use all navigation system together to provide better capabilities compared with those that would be achieved relying solely on one service or signal. Compatibility, on the other hand, assures that existing GNSS signal is not degrading each other below certain threshold. GNSS provider is concerned about their own signal as well as other signals from different service provider for co-existence. For this reason interference analysis of current GNSS signal is the most needed requirement in current scenario. India is developing its own regional navigation systems named as Indian Regional Navigation Satellite System (IRNSS).An in-house tool is developed with suitable Graphic User Interface (GUI) which provides static analysis of different type of interference parameters and indicates its compatibility with already existing signals. Using the tool, this...
Precise determination of the metallic rubidium (Rb) inside a Rb bulb is critical to the life of o... more Precise determination of the metallic rubidium (Rb) inside a Rb bulb is critical to the life of on-board RAFS. Calorimetric mass estimation is an accurate and non-destructive method to validate the Rb content, without deforming the glass bulb under test. We present a faithful and precise calorimetric method using an indigenous cold-point-formation apparatus (CPA), which efficiently collects the metallic Rb in the glass bulb for a precise calorimetric estimation (±20μg\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\pm 20 \mu g$$\end{document}). We have also performed repeated mass estimations with our calorimetric method revealing a maximum estimation difference only of about 10μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$10\,\mu$$\end{document}g. Further, with the ongoing life test of five Rb bulbs, we report a preliminary estimate of Rb consumption rate inside our bulbs as 0.64 μg/hr\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu g/\sqrt{h}r$$\end{document}, which is in good agreement with the previously reported results.
NavIC (Navigation with Indian Constellation) is a regional satellite navigation system called Ind... more NavIC (Navigation with Indian Constellation) is a regional satellite navigation system called Indian Regional Navigation Satellite System (IRNSS). The NavIC is presently composed of seven operational satellite configuration geometry. We present indigenously designed and developed RAFS for NavIC, named IRAFS—Indian Rubidium Atomic Frequency Standard. The IRAFS Physics Package (PP) and electronics have novel design features, as explained in this article. We present the IRAFS performances tested in thermo-vacuum conditions demonstrating < 2 × 10–12τ−1/2 stability, reaching a flicker floor of 3 × 10–14 with a drift of < 5 × 10–13/day. The IRAFS has a mass of 7.6 kg, a volume of 16 L, and consumes power of 75 W at warm-up and < 40 W in normal operation.
Advanced satellite communication systems should be capable of preventing unauthorized access or e... more Advanced satellite communication systems should be capable of preventing unauthorized access or exploitation of communication services by adversaries. This can be achieved by use of wideband multi-channel digital transceivers which employ channelizer to extract the channel of interest from digitized RF bands for further baseband processing. Various anti-jamming techniques like Frequency hopping are used to prevent the systems from intentional jamming by the hostile systems. This paper presents an efficient channelizer architecture which supports wideband as well as narrowband channels with programmable channel bandwidth followed by frequency hopping for the proposed SATCOM system. The target design is a flexible channelization unit which divides the incoming data links of 11 MHz bandwidth into two data links in granularity of 0.5 MHz depending upon user requirements. First link is further sub-channelized into two sub-links each having a bandwidth of 25 KHz that is frequency hopped a...
Noise estimation of atomic clock is one of the important research areas in the field of atomic cl... more Noise estimation of atomic clock is one of the important research areas in the field of atomic clock development and application. Most of the atomic clocks are having random-stochastic noises and periodic noises due to temperature variation. Random-stochastic noises have a well identified signature in time domain but periodic noises are difficult to analyze in time domain. However, in this paper, an effort is made to identify and analyze the deterministic trends of both random-stochastic noises and periodic noises due to variation in temperature using an alternate approach of least-squares normalized-error (LSNE) regression algorithm. A MATLAB based application with graphical user interface (GUI) is developed to estimate and analyze random-stochastic noises and periodic noises and re-estimate the stability of rubidium atomic clock after removing these noises from the raw phase data. The estimation of stationary noises are done using Allan variance from time domain data and noise pro...
2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), 2016
This paper describes the design and in-house development of FPGA based Digital Beam Forming Hardw... more This paper describes the design and in-house development of FPGA based Digital Beam Forming Hardware for 16 elements configuration. Key function of the System involves electronic steering of beam in desired direction to provide anti-jamming feature in communication and navigation satellites. This system has capability to maximize the received power in the direction of signal of interest & minimize the power in the direction of interference. Digital down conversion (DDC) technique is incorporated in the design for providing flexible channel architectures. Dynamic phase calibration and weight uploading facility is included to provide beam forming capability in real time without any hardware penalty.
This paper presents the design and implementation of an effective Single Event Upset (SEU) mitiga... more This paper presents the design and implementation of an effective Single Event Upset (SEU) mitigation technique for radtolerant Xilinx virtex-4xqr4vsx55FPGA used in Digital Bandwidth Efficient Filter (DBEF) subsystem for a Geostationary mission. The Single Event Effects (SEE) on the virtex-4FPGA are minimized using an external scrubbing engine, which is implemented using rad-hard RTSX32SU-CQ84 Actel FPGA. The availability and reliability analysis shows an optimum window for performing scrubbing function in Geo-stationary earth orbit.
2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016
An open standard compatible onboard processing system is under development, which provides mesh c... more An open standard compatible onboard processing system is under development, which provides mesh connectivity between different user terminals. The system is designed to be compatible to Digital Video Broadcasting - Return Channel via Satellite (DVB-RCS) protocol in uplink and Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) in downlink channels. Due to widespread use of this protocol in DTH, low cost compatible terminals are widely available in market. The main elements of this system are DVB-RCS burst demodulator and decoder, protocol convertor, baseband processor with channel estimator and DVB-S2 modulator. This work presents the architecture of baseband processing and channel estimation module. So this requires advanced micro-controller and fast digital signal processor. Also this processor can be time shared for timing recovery module of burst demodulator. Since the system is designed to be implemented as an onboard processor (OBP) for communication satellite, therefore LEON-3 processor and Digital Signal Processor (DSP) SMJ320C6701 are chosen due to availability of their radiation tolerant versions. This paper presents an interface between LEON-3 and DSP for faster execution of both base band processing and floating point operations. Simulation of interface is done on ModelSim® and performance evaluation and comparison has been done on simulators. TSIM2 simulator is used to simulate LEON-3 where as to simulate DSP SMJ320C6701, Code Composer Studio v5 is used.
The communication links at high speed requires bit synchronizer for countering bit phase misalign... more The communication links at high speed requires bit synchronizer for countering bit phase misalignment at the receive end. This paper describes the design of IC based digital bit synchronizer for high speed optical communication links. It supports data rate from 10 Mbps to1 Gbps. The design shows the excellent jitter and eye performance with an eye opening of 95.5% at data rate of 1Gbps. The test results shows that worst case total root mean square jitter is 28.6 picoseconds exceeding the nominal standards of SONET jitter requirements.
2013 Third International Conference on Advances in Computing and Communications, 2013
In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports va... more In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports variable data rates varying from 4.88Kbps to 2Mbps and higher is described. The paper presents the design of carrier and symbol recovery loops in details. The design is made platform independent so that it can be ported to any FPGA device. Proposed design is targeted for Xilinx Virtex-II pro FPGA xc2vp50-6ff 1152 for Hardware proof of concept. The complete demodulator occupies only 13% of the available logic slices in Xilinx Virtex-II pro FPGA device.
2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems, 2009
The Base Band Processor and Switching System is one of the important Subsystem of GSAT-4 satellit... more The Base Band Processor and Switching System is one of the important Subsystem of GSAT-4 satellite. This paper discusses unique approach to handle multiple interrupts on system having constraint on limited external interrupts of micro-controller. The system also has to be optimized with limited resources available on board in terms of memory, power consumption and speed. This is an embedded system with program development in assembly language with careful selection of hardware and software partition of system. GSAT-4 Ka band payload with Regenerative transponder is a unique mission in the history of Indian Space Program. This Regenerative payload will lead ISRO into a new era of Advanced Communication Satellite Systems.
2014 International Conference on Signal Processing and Integrated Networks (SPIN), 2014
Automatic identification of the digital modulation type of asignal has found applications in many... more Automatic identification of the digital modulation type of asignal has found applications in many areas, including software defined radio (SDR), surveillance and threat analysis. This paper describes the FPGA based implementation of Automatic Modulation Recognition (AMR) algorithm foradvanced communication payload. A wavelet transform based algorithm which involves multi-rate signal processing, is realizedto distinguish QAM, PSK and FSK digital modulation signal in noisy environment. The approach is to use wavelet transform to extract the transient characteristics ina digital modulation signal to identify the type of modulation. The optimum thresholds are derivedfrom rigorous simulation in MATLAB/Simulinkunder the condition that the input noise is Additive WhiteGaussian (AWGN). The performance of the identification schemeis investigated through simulations. The design is implemented and tested in Xilinx Virtex-4 FPGA based card.
In satellite communication deep space mission are the most challenging mission, where system has ... more In satellite communication deep space mission are the most challenging mission, where system has to work at very low Eb/No. Concatenated codes are the ideal choice for such deep space mission. ISRO is planning to send unmanned mission for Mars and several deep space missions in future to study and detailed understanding of our own universe. This paper basically reviews the concatenated convolutional code structure and selects the suitable candidate for our future deep space mission. The complete simulation using Simulink is done and results are presented in this paper.
2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), 2019
This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC... more This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC) encoder for DVB S2 system which includes BCH code followed by LDPC code and finally bit mapped to constellation for QPSK modulation. DVB-S2 FEC: ($\mathbf{n}=64800,\ \mathbf{k}=32400$) rate 1/2 code, with QPSK modulation scheme is considered as target for FPGA implementation. The architecture in this design efficiently uses pipeline technique along with parallel processing to optimize the hardware resources and overall latency, to accomplish FEC encoding for DVB S2 system. Coding is completed in Verilog HDL with Xilinx Virtex6 XC6VLX240T FPGA as target for hardware realization and QuestaSim simulator is used to complete the functional simulation.
In many low-noise applications, extracting information from the extremely noisy signal is require... more In many low-noise applications, extracting information from the extremely noisy signal is required. This task can be accomplished by a lock-in amplifier if the frequency of the signal is known before detection. Error signal output from the physics package of the rubidium atomic clock (RbAC) is one of those noisy signals. A lock-in amplifier extracts the desired information from such a signal as the frequency of the error signal is known beforehand. The Space Applications Centre of the Indian Space Research Organisation is developing the Indian Rubidium Atomic Frequency Standard (IRAFS) for Navigation with Indian Constellation. We have developed a digital lock-in amplifier with a very high-resolution frequency control voltage for IRAFS. This paper demonstrates the digital lock-in amplifier with a novel method of combining two 12-bit digital-to-analog converters (DACs) to get higher resolution 20-bit output for precise frequency control and tuning. This design technique allows a digital lock-in amplifier to be used for high-performance RbAC for space applications as precision DACs with higher resolution are not available in space-qualified versions.
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