Abstract: Consumer electronics vendors increasingly deploy shared-memory multiprocessor SoCs, suc... more Abstract: Consumer electronics vendors increasingly deploy shared-memory multiprocessor SoCs, such as Philips Nexperia, to balance flexibility (late changes, software download, reuse) and cost (silicon area, power consumption) requirements. With the convergence of storage, digital television, and connectivity, these media-processing systems must support numerous operational modes. Within a mode, the system concurrently processes many streams, each imposing a potentially dynamic workload on the scarce system resources. The dynamic sharing of scarce resources is known to jeopardize robustness and predictability. Resource reservation is an accepted approach to tackle this problem. This chapter applies the resource reservation paradigm to interrelated SoC resources: processor cycles, cache space, and memory access cycles. The presented virtual platform approach aims to integrate the reservation mechanisms of each shared SoC resource as the first step towards robust, yet flexible and cos...
Start date of project: 1 April, 2014 Duration: 36 months Organisation name of lead contractor for... more Start date of project: 1 April, 2014 Duration: 36 months Organisation name of lead contractor for this deliverable: Vector Fabrics BV Author(s): Jos van Eijndhoven, Toygar Akgün, Pekka Jääskeläinen, Zdenek Pohl Validated by: Pekka Toivanen Version number: 1.2 Submission Date: Oct. 10, 2015 Doc reference: ... Work Pack./ Task: WP 3, Task 3.3 Description: (max 5 lines) The report provides the description on how to interface and integrate application-level concurrency on multi-core processors and heterogeneous acceleration fabrics: a software layer abstracts from details in the target hardware architectures, enabling re-use through design methods, tools, and libraries.
This paper proposes architectural solutions that deal with two of the most crucial performance re... more This paper proposes architectural solutions that deal with two of the most crucial performance requirements imposed by the MPEG-4 standard, namely high data throughput and high computational power. To obtain higher data throughput, we define a new data storage facility with a specific data organization and a new addressing mode called two-dimensional block addressing. To achieve higher computational power, we propose an instruction set extension, bene tting from this addressing mode. This is illustrated by the implementation of a new instruction called "ACcepted Quality" (ACQ). This instruction supports the identically named ACQ function, which is an essential part of the shape encoding process in MPEG-4. We have implemented the ACQ function on a dedicated systolic structure and its FPGA realization suggests 62 ns operating latency. Utilizing this result, we have made performance evaluations with a benchmark software (MPEG-4 shape encoder) by a cycle-accurate simulator. Th...
Disclaimer This document contains a student thesis (bachelor's or master's), as authored ... more Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration.
We present an instruction-level power dissipation model of the Intel XScale microprocessor. The X... more We present an instruction-level power dissipation model of the Intel XScale microprocessor. The XScale implements the ARM ISA, but uses an aggressive microarchitecture and a SIMD Wireless MMX co-processor to speed up execution of multimedia workloads in the embedded domain. Instruction-Level power modelling was first proposed by Tiwari et. al in 1994. Adaptations of this model have been found to be applicable to simple ARM processors. Research also shows that instructions can be clustered into groups with ...
Asia and South Pacific Design Automation Conference, 2002
Summary form only given. Reports on system-level design practices in Philips. First we present th... more Summary form only given. Reports on system-level design practices in Philips. First we present the design problems encountered in the development of embedded media systems for the consumer market. The characteristics and requirements of the consumer electronics domain are presented. We focus on high performance video applications and the demands that these applications put on architectures of embedded media systems.
This tutorial reports on system-level design practices in Philips. First we present the design pr... more This tutorial reports on system-level design practices in Philips. First we present the design problems encountered in the development of embedded media systems for the consumer market. The characteristics and requirements of the consumer electronics domain are presented. We focus on high performance video applications and the demands that these applications put on architectures of embedded media systems. Several high performance embedded systems architectures are illustrated. This includes an in depth discussion of high performance programmable components, in which the TriMedia VLIW cores are taken as an example. We further discuss system-on-a-chip (SoC) architectures that incorporate such cores. We address the aspect of heterogeneous SoC architectures that incorporate components in the range from programmable processors to function-specific hardware engines. For such architectures trade-offs can be made with respect to flexibility, performance, and cost to implement an optimal sol...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystem... more New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, relying on abstraction from implementation details. These chips will support the execution of a mix of concurrent applications that are not known in detail at chip design time. These SoCs require a significant degree of programmability to configure both the set of functions that must execute as well as the structure of the dataflow between these functions. To ease the programming effort multiprocessor computers have employed cache coherent share memory for decades, abstracting the average programmer from system complexity issues such as multiple processors and memory hierarchies. Memory coherency in multiprocessor computers has a history of decades, and has proven to be an indispensable abstraction from system complexity towards the application programmer. This chapter describes a next generation SoC for the consumer electronics domain (e.g. audio/video, vision, robotics). It features...
Abstract: Consumer electronics vendors increasingly deploy shared-memory multiprocessor SoCs, suc... more Abstract: Consumer electronics vendors increasingly deploy shared-memory multiprocessor SoCs, such as Philips Nexperia, to balance flexibility (late changes, software download, reuse) and cost (silicon area, power consumption) requirements. With the convergence of storage, digital television, and connectivity, these media-processing systems must support numerous operational modes. Within a mode, the system concurrently processes many streams, each imposing a potentially dynamic workload on the scarce system resources. The dynamic sharing of scarce resources is known to jeopardize robustness and predictability. Resource reservation is an accepted approach to tackle this problem. This chapter applies the resource reservation paradigm to interrelated SoC resources: processor cycles, cache space, and memory access cycles. The presented virtual platform approach aims to integrate the reservation mechanisms of each shared SoC resource as the first step towards robust, yet flexible and cos...
Start date of project: 1 April, 2014 Duration: 36 months Organisation name of lead contractor for... more Start date of project: 1 April, 2014 Duration: 36 months Organisation name of lead contractor for this deliverable: Vector Fabrics BV Author(s): Jos van Eijndhoven, Toygar Akgün, Pekka Jääskeläinen, Zdenek Pohl Validated by: Pekka Toivanen Version number: 1.2 Submission Date: Oct. 10, 2015 Doc reference: ... Work Pack./ Task: WP 3, Task 3.3 Description: (max 5 lines) The report provides the description on how to interface and integrate application-level concurrency on multi-core processors and heterogeneous acceleration fabrics: a software layer abstracts from details in the target hardware architectures, enabling re-use through design methods, tools, and libraries.
This paper proposes architectural solutions that deal with two of the most crucial performance re... more This paper proposes architectural solutions that deal with two of the most crucial performance requirements imposed by the MPEG-4 standard, namely high data throughput and high computational power. To obtain higher data throughput, we define a new data storage facility with a specific data organization and a new addressing mode called two-dimensional block addressing. To achieve higher computational power, we propose an instruction set extension, bene tting from this addressing mode. This is illustrated by the implementation of a new instruction called "ACcepted Quality" (ACQ). This instruction supports the identically named ACQ function, which is an essential part of the shape encoding process in MPEG-4. We have implemented the ACQ function on a dedicated systolic structure and its FPGA realization suggests 62 ns operating latency. Utilizing this result, we have made performance evaluations with a benchmark software (MPEG-4 shape encoder) by a cycle-accurate simulator. Th...
Disclaimer This document contains a student thesis (bachelor's or master's), as authored ... more Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration.
We present an instruction-level power dissipation model of the Intel XScale microprocessor. The X... more We present an instruction-level power dissipation model of the Intel XScale microprocessor. The XScale implements the ARM ISA, but uses an aggressive microarchitecture and a SIMD Wireless MMX co-processor to speed up execution of multimedia workloads in the embedded domain. Instruction-Level power modelling was first proposed by Tiwari et. al in 1994. Adaptations of this model have been found to be applicable to simple ARM processors. Research also shows that instructions can be clustered into groups with ...
Asia and South Pacific Design Automation Conference, 2002
Summary form only given. Reports on system-level design practices in Philips. First we present th... more Summary form only given. Reports on system-level design practices in Philips. First we present the design problems encountered in the development of embedded media systems for the consumer market. The characteristics and requirements of the consumer electronics domain are presented. We focus on high performance video applications and the demands that these applications put on architectures of embedded media systems.
This tutorial reports on system-level design practices in Philips. First we present the design pr... more This tutorial reports on system-level design practices in Philips. First we present the design problems encountered in the development of embedded media systems for the consumer market. The characteristics and requirements of the consumer electronics domain are presented. We focus on high performance video applications and the demands that these applications put on architectures of embedded media systems. Several high performance embedded systems architectures are illustrated. This includes an in depth discussion of high performance programmable components, in which the TriMedia VLIW cores are taken as an example. We further discuss system-on-a-chip (SoC) architectures that incorporate such cores. We address the aspect of heterogeneous SoC architectures that incorporate components in the range from programmable processors to function-specific hardware engines. For such architectures trade-offs can be made with respect to flexibility, performance, and cost to implement an optimal sol...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystem... more New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, relying on abstraction from implementation details. These chips will support the execution of a mix of concurrent applications that are not known in detail at chip design time. These SoCs require a significant degree of programmability to configure both the set of functions that must execute as well as the structure of the dataflow between these functions. To ease the programming effort multiprocessor computers have employed cache coherent share memory for decades, abstracting the average programmer from system complexity issues such as multiple processors and memory hierarchies. Memory coherency in multiprocessor computers has a history of decades, and has proven to be an indispensable abstraction from system complexity towards the application programmer. This chapter describes a next generation SoC for the consumer electronics domain (e.g. audio/video, vision, robotics). It features...
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