Ternary Łukasiewicz logic using memristive devices

Table 3 shows the different resistance states required for the RESET direction Łukasiewicz logic simulated in the 1 R structure. The resistance values and states of the adder in the 1S1R structure are shown in table 7. For the ternary logic, only the states LRS, R₀ and R₁ are required, while the adder requires one more state R₂. Next to the experimental resistance values, the simulated values are shown that result from the fitted JART VCM model v1b [34]. Additionally, the assignment of resistances to logic states and their mapping to voltage levels as well as the required total device voltages is shown. Implication and negation consist of three steps each, first an initialization into the LRS, second the application of the voltages according to the different mapping schemes for implication and negation and third a read out of the device state.

3.1.1. Negation

The result of the negation operation of p, which is $\neg$p, depends on the initial state of the cell. While an initial resistance level R₀ (logical state 1) is mapped unto itself, the resistance level LRS (logical state 0) is mapped to R₁ (logical state 2) and vice versa, R₁ is mapped to the LRS. The negation is shown in figure 3. (a) shows the voltages applied at the AE as differently colored solid lines and the OE voltage is shown as dashed black line. In (b) the resistance transients are shown that are calculated based on the values of the state variable $N_{\mathrm{disc}}$. For that purpose, the cell is first initialized into the LRS by applying −1 V at the AE and 1 V at the OE, $V_{\mathrm{logic}}$ is chosen according to table 3 and $V_{\mathrm{offset}}$ is chosen as 1.5 V (corresponding to the required $V_{\mathrm{device}}$ for the resistance state which is mapped to the logic state 1). Half of $V_{\mathrm{offset}}$ is applied at the AE and half is applied negated at the OE. After the initialization, $V_{\mathrm{device}} = V_{\mathrm{offset}}+V_{\mathrm{p}}$ is applied. In the last step the result is read out by applying −0.1 V. From the colors we can see that the in the case of p = 2 the resistance is actually larger than the nominal LRS resistance due to a limited switching at a device voltage of −1.35 V. Therefore, all resistances below the R₀ level have to be interpreted as belonging to the LRS.

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3.1.2. Implication

The implication $p\rightarrow q$ also consists first of an initialization into the LRS, then a logic step and finally a read out step. It is performed in three steps as shown in figure 4. As for the negation, (a) shows the voltage schemes, with the solid lines displaying the AE voltage and the dashed line displaying the OE voltage. (b) shows the resistance trace calculated based on the current and voltage results. First, the targeted cell is initialized in the LRS by applying a −1 V at the AE and 1 V at the OE. In the RESET step, $V_{\mathrm{offset}}/2+V_{\mathrm{logic, p}}$ and $-V_{\mathrm{offset}}/2+V_{\mathrm{logic, q}}$ are applied at the AE and OE, respectively. For the implication operation, $V_{\mathrm{offset}}$ is always 1.35 V, while the logical input states p and q are again converted using table 3. Lastly, the result is read out by applying a small read voltage of −0.1 V to the AE while the OE is grounded. In figure 4 q is always 2 and p is 2 (petrol line), 1 (light blue line), and 0 (dark green). Therefore, the OE voltage is always −0.675 V+(−0.15 V) = −0.825 V, while the AE voltage changes from 0.525 V for p = 2, to 0.825 V for p = 0.

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This section focuses on the Ł₃ logic implementation utilizing the SET process of the mentioned VCM device. The logic states for the Ł₃ logic are listed in table 4. The simulation results indicate a tolerance with ±0.01 V of the required voltage drop $V_{\mathrm{gs}}$. For example, the simulation ranging from 4.23 MΩ to 4.7 MΩ corresponds to the $V_{\mathrm{gs}}$ ranging from 0.51 V to 0.49 V. For HRS, without strong enough driving force $V_{\mathrm{gs}}$, the device cannot be programmed to lower resistive states. When the tolerances are taken into consideration, the HRS is equal to or larger than the resistance corresponding to $V_{\mathrm{gs}} = 0.51$ V. In the following simulations, the device is always initialized with a 3 V RESET voltage applied to the source of the transistor and SET with a 4 V SET voltage along with the logical inputs being applied to the OE of the device. Unlike utilizing absolute voltage drops over the device in RESET operation, computing in SET operation needs a sufficient voltage drop across the device considering the voltage divider effect with the transistor. In addition, the switching process is mainly controlled by the voltage drop across the gate and source of the transistor. With a variable gate-source voltage drop over the transistor the drain saturation current flowing through the device is tuned to limit the SET operation. The larger the $V_{\mathrm{gs}}$, the wider opens the transistor, so that the lower resistive states can be reached in the device. According to the schematic shown in figure 1(d), the gate-source voltage drop over the transistor during the SET process is given as:

$\begin{equation} V_{\mathrm{gate}} = V_{\mathrm{offset}} + V_{\mathrm{logic,input,p}} \end{equation} \tag{ 6 }$

$\begin{equation} V_{\mathrm{source}} = V_{\mathrm{logic,input,q}} \left(+ V_{\mathrm{logic,input,c}}\right) \end{equation} \tag{ 7 }$

$\begin{equation} V_{\mathrm{gs}} = V_{\mathrm{gate}} - V_{\mathrm{source}} = V_{\mathrm{offset}} +V_{\mathrm{logic,input,p}}-V_{\mathrm{logic,input,q}} \left( - V_{\mathrm{logic,input,c}}\right). \end{equation} \tag{ 8 }$

Table 4. Simulated resistance states and their assignment in the different Łukasiewicz logic. The rightmost column shows the required absolute programming voltages $V_{\mathrm{gs}}$ required to reach the specific level.

States	Sim. Range	Sim.	Ł3	$V_{\mathrm{logic}}$	$V_{\mathrm{gs}}$
HRS	($\unicode{x2A7E}$)4.23–4.7 MΩ	4.48 MΩ	0	0.1 V	0.5 V
MRS	2.43–3.27 MΩ	2.87 MΩ	1	0.05 V	0.55 V
LRS	0.25–0.97 MΩ	0.55 MΩ	2	0 V	0.6 V

When using only two operands, they can be applied to the gate and source separately. With three operands the third one is linked into the source side, as presented in the parentheses as logic input c. The voltage at the OE terminal is as follows:

$\begin{equation} V_{\mathrm{OE}} = V_{\mathrm{SET}} + \alpha * V_{\mathrm{source}} \end{equation} \tag{ 9 }$

where α is a coefficient for adjusting the effective voltage drop over the device. It is associated with the chosen resistances in the device and the resistance of the transistor because of the voltage divider effect. For the resistances in the MΩ range and the applied transistor in this work, it is set to 1.62. In other cases, the optimal α can be found through simulation as well. Since the logic states are linked to the gate-source voltage drop, the logical inputs can be converted into the voltage inputs at the gate and source of the transistor. To better represent the logical states and the voltage inputs, offset voltages ($V_{\mathrm{offset}}$) are used in this concept as well, which are integrated into the gate voltages of the transistor (cf equation (6)). The offset voltages are chosen as 0.5 V in order to match the programming voltages $V_{\mathrm{gs}}$ in table 4, so that the other logical inputs can be mapped to the corresponding voltage levels. As shown in the schematic, $V_{\mathrm{gate}}$ is applied to the gate of the transistor and $V_{\mathrm{source}}$ to the source terminal. The mapping of the voltage inputs with the logic states are shown in table 4. It is clearly evident that the difference(Δ) between logic states or voltage inputs is constant. After mapping the pair of starting states, the following mapping can be achieved with counting the number of the increasing levels Δs. For example, when logic 0 was mapped to $V_{\mathrm{logic,start}} = 0~\textrm{V}$, for logic 1 it has two increased Δs so that the corresponding $V_{\mathrm{logic}}$ should be added with two level states ($2*0.05$ V) from the starting level 0 V, resulting in 0.1 V. This concept is easy to be extended to higher multi-valued logic.

3.2.1. Negation

The definition of the negation operation has been described in the previous section. Firstly the device will be programmed to the HRS. Then, the device is programmed to the desired output state by applying suitable voltages $V_{\mathrm{gs}}$ and $V_{\mathrm{source}}$. As there is only one input for the negation operation, i.e. p, $V_{\mathrm{logic,input,q}}$ is set to 0 V. When performing the Ł₃ negation operation with the SET process, to maintain the mirroring effect around the middle value, the middle logical voltage input $V_{\mathrm{gs}}$ has to be mapped with the middle logic value (1) which means $V_{\mathrm{gs}} = 0.55\,\mathrm{V}$ coupled with $V_{\mathrm{logic,input,p}} = 1$. By setting the $V_{\mathrm{offset}}$ to 0.5 V, $V_{\mathrm{p = 1}}$ must be $V_{\mathrm{gs}}$ minus $V_{\mathrm{offset}}$, resulting in 0.05 V. With mapping the interval of logic level to 0.05 V of the voltage input, the $V_{\mathrm{p}}$ is linked to $\mathrm{logic}_{\mathrm{p}}$ in an opposite direction. While $\mathrm{logic}_{\mathrm{p}} = 2$ increases from $\mathrm{logic}_{\mathrm{p}} = 1$ by 1, $V_{\mathrm{p}} = 0~\mathrm{V}$ decreases from $V_{\mathrm{p}} = 0.05~\mathrm{V}$ by 0.05 V. The mapping for $\mathrm{logic}_{\mathrm{p}} = 0$ can be achieved similarly, resulting in $V_{\mathrm{p}} = 0.1~\mathrm{V}$. By coding the read out states of resistances with logic values and voltage inputs the mapping is achieved in the end and shown in table 5.

Table 5. Mapping of the logical input states to the equivalent voltage levels for the negation operation and the simulated final results of the negation operation.

logicp	Vp	$V_{\mathrm{offset}}$	$\neg$p	Read out $R_{\mathrm{device}}$
0	0.1 V	0.5 V	2	0.55 MΩ
1	0.05 V	0.5 V	1	2.87 MΩ
2	0 V	0.5 V	0	4.48 MΩ

Figure 5(a) shows the three voltage input signals at the gate and the source of the transistor and the OE of the device. Figure 5(b) is the gate-source voltage drop on the transistor. The simulation results of the negation operation is shown in figures 5(c) and (d). Compared with the states shown in figure 2, the marked colors are exactly in the opposite direction and the final read out resistances are listed in table 5.

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3.2.2. Implication

The operation of the implication in the SET direction consists of three steps as well: RESET-initialization, logic computing or programming and read out. The RESET and read out procedure are the same as in the negation operation in last subsection, while the logic computing step differs. First of all, the logic input q is converted into a voltage level and added to the source voltage. The offset voltage $V_{\mathrm{offset}}$ in the gate voltage is set to 0.5 V corresponding to the $V_{\mathrm{gs}}$ for achieving HRS. In this operation, $V_{\mathrm{logic,q}}$ is no longer 0 V, so that the $V_{\mathrm{gs}}$ is exactly the same as given in equation (8). Like the programming voltage curve in last negation section, the applied voltage input signals and $V_{\mathrm{gs}}$ are presented in figures 6(a) and (b), respectively. During the implication operation, $V_{\mathrm{gs}}$ has 5 levels in the SET programming procedure, two of which are able to switch the device into lower resistive states, MRS and LRS, marked in orange and red, respectively. The other three blue lines represent the HRS. As discussed before, all read out resistances larger than 4.28 MΩ are considered as HRS (blue). The resulting resistances are shown in figures 6(c) and (d) presents the corresponding concentration of oxygen vacancies in the disc. The mapping of the voltage levels to the logic inputs of this operation is shown in table 4.

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The final simulation result of the implication is shown in table 6. The color in the background together with the logic value of p and q verify the truth table of the implication logic operation. Because of the read out procedure, the applied limit for the HRS is set to 0.5 V as before. Therefore, the read out resistance for p = 0 and q = 2 should be 2 levels larger than the corresponding resistances (4.48 MΩ) and this is verified in the table.

Table 6. Simulation results of $p\rightarrow q$ for Ł₃ in SET progress.

$q\backslash p$	2	1	0
2	4.48 MΩ	2.87 MΩ	0.55 MΩ
1	5.33 MΩ	4.48 MΩ	2.91 MΩ
0	5.68 MΩ	5.33 MΩ	4.47 MΩ

The ternary adder demonstrated here is adapted from the scheme introduced in [28]. While in [28] six HRS levels were required, we show how this can be reduced to three HRS by using a constant offset reduction. The flow chart of the adder operation is shown in figure 7(a) for the ith bit position. To perform the addition for one bit position only one cell is required. Additionally, the carry from the previous stage (i − 1) has to be stored, as it determines the offset voltage. The addition is then performed in the following way. First, the ith cell is initialized into the LRS. For that purpose, the SET voltage of −4.5 V is split equally between the OE and the Bitline. Then, depending on the carry output of the previous stage ($c_{\mathrm{i}}$) the offset is either chosen as 1.825 V (if $c_{\mathrm{i}} = 0$) or 1.875 V (if $c_{\mathrm{i}} = 1$). Next, the cell is RESET based on the chosen offset voltage and the converted logical inputs. The RESET voltages are in the range 3.65 V–3.85 V with a 0.1 V spacing between the different levels. The resistances R₀, R₁ and R₂ are used to represent the logic levels 0, 1 and 2, respectively. The operands of the addition are encoded as voltages ($V_{\mathrm{op, i}}$), with a logical zero being mapped to 0 V, logical 1 being mapped to 0.1 V and logical 2 being mapped to 0.2 V, corresponding to the spacing of the RESET voltages. The first operand is applied to the BL $V_{\mathrm{BL}}$ = −($V_{\mathrm{offset}}+V_{\mathrm{op, 1}}$) and the second operand together with the offset voltage is applied to the OE $V_{\mathrm{OE}} =$($V_{\mathrm{offset}}+V_{\mathrm{op},2}$). The resulting device voltage is then given as $V_{\mathrm{device}} = V_{\mathrm{BL}}-V_{\mathrm{OE}} = -2V_{\mathrm{offset}}-V_{\mathrm{op}, 1}-V_{\mathrm{op}, 2}$. A voltage increment of 0.1 V corresponds to a logical increment of 1. Directly after the RESET, the cell is read out at −1.7 V applied at the OE. The resistance state of the read out cell is then compared with R₂. If it is smaller or equal to R₂, the carry for the next stage $c_{\mathrm{i}+1}$ is zero and the sum bit at position i is equal to the cell resistance. If the resistance of the cell is larger than R₂, $c_{\mathrm{i}+1}$ is one and the cell has to be reprogrammed. For that purpose, first the offset voltage is reduced by 0.3 V. Then, the cell is SET, RESET with the adapted offset voltage and read out again. The new read resistance is then the sum bit $s_{\mathrm{i}}$. For a 41 Trit addition, 42 devices are required as one device is needed to store the carry output of the 41st stage.

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Due to the program disturb effect in m·n arrays, where m and n are both larger than one, a selector element is required for each device to prevent read disturb. The 1S1R array structure is shown in figure 7(b), with three devices that are connected with each other via a single OE. Each device has an individual BL and the device direction is defined, such that the SET occurs at negative $V_{\mathrm{device}}$ and the RESET occurs at positive $V_{\mathrm{device}}$. To make the adder scheme array compatible a selector element is added in series to the VCM cell and the voltages are split between OE and Bitlines, similar as for a V/2 scheme. Adding the selector requires an increase in the required voltages compared to the initial demonstration in [28]. Figures 7(c)–(e) show the OE voltages (red solid lines) and BL voltages (black dashed lines) of the different devices. The final current levels can be seen in figures 7(f)–(h). They are also summarized in table 7.

Table 7. Resistance definitions and current levels of the different states in the 1S1R array at the read voltage of −1.7 V applied to the OE with the bitline being grounded. The rightmost column shows the voltage required to program the corresponding state in the 1S1R array.

State	Resistance	Current	$V_\mathrm{Device}$
LRS	10.8 kΩ	158 µA	−4.5 V
R0	27.4 kΩ	62 µA	3.65 V
R1	100 kΩ	17 µA	3.75 V
R2	217.9 kΩ	7.8 µA	3.85 V

The SET phase of the addition is encoded in orange, the RESET phase is encoded in green and the read phase in blue. SET and read phase are always performed in the same way, only the RESET phase changes based on the current operand voltages and the offset. The x-axis is scaled to highlight the interesting section for each cell for the first cell (c) and (f), the middle cell (d) and (g) and the last cell (e) and (h). The final resistances of the three devices shown are R₂ for the first device, R₀ for the 22nd device and R₁ for the last device. If the addition has finished for a certain cell, the corresponding BL is set to ground and the cell only sees around half of the operating voltage via the OE. Due to the selector device in series this does not lead to unwanted switching anymore.

With the same parameter set given in table 1 a ternary adder can be implemented in the SET process as well. This concept is also based on the modulo sum operation. Besides the three resistive states presented in table 4 additional space for the read out resistances smaller than LRS is essential for judging the carry Trit. This state does not have to and will not be stored in the end, therefore it is named as TRS (temporary resistive state). TRS is naturally defined in the range $\lt0.25$ MΩ. To represent the logic values, HRS, MRS, LRS and TRS are mapped to sum Trit as 0, 1, 2 and carry bit as 1, respectively. All the relationships of the inputs are given in the following equations:

$\begin{equation} V_{\mathrm{gate}} = V_{\mathrm{offset}} + V_{\mathrm{p}}+0.15\mathrm{V} \end{equation} \tag{ 10 }$

$\begin{equation} V_{\mathrm{source}} = 0.15 {\text{V}} - V_{\mathrm{q}}- V_{\mathrm{c}} \end{equation} \tag{ 11 }$

where 0.15 V is used to keep the source voltage positive and it should be compensated in the gate voltage as well and $V_{\mathrm{OE}} = V_{\mathrm{SET}} + \alpha* V_{\mathrm{source}}$ offers the driving force in the switching process. The operands $V_{\mathrm{p}}$ and $V_{\mathrm{q}}$ of the operation are embedded in the gate and the source voltage of the transistor, respectively. Meanwhile, an offset voltage is needed as well to tune the $V_{\mathrm{gs}}$ for achieving the expected resistive states in the device. The voltage input $V_{\mathrm{c}}$ for the carry bit is added to the source (and OE) voltage, serving as the 3rd operand

$\begin{equation} V_{\mathrm{gs}} = V_{\mathrm{gate}} - V_{\mathrm{source}} = V_{\mathrm{offset}} +V_{\mathrm{p}}+V_{\mathrm{q}}+V_{\mathrm{c}}. \end{equation} \tag{ 12 }$

This equation perfectly represent the additive operation with three operands. Only the carry has to be considered and realized in an extra operation step. The mapping of the logic values to the voltage levels are given in table 4. It is clear that $V_{\mathrm{c}}$ depends on the previous operation and because of the procedure of the judgement in between: whether the read out resistance equals to or is lower than TRS, it is required to run the RESET-SET-READ-cycle twice for a single Trit sum operation, which are named as pre-sum and end-sum here. In case the carry of the current sum operation was 1, the end-sum operation has to implemented with a new offset voltage, 0.15 V lower, as shown in the flow diagram in figure 8(a). All devices have to be operated with the pre-offset voltage in the first operation cycles. Is the read out resistance lower than TRS, the device has to be operated again with the end-offset voltage (0.15 V lower than pre-offset voltage) for the end-sum, meanwhile the carry for the next Trit will be set to 1, otherwise it will be 0. Theoretically, when the carry equals to 0, the second sum operation could be avoided, but for the universal computation logic this step is still preserved in this concept. Furthermore, while performing the end-sum operation for the last Trit the pre-sum operation of the current Trit could be performed simultaneously. Therefore, an n-Trit addition operation takes n+1 cycles.

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A part of the 41 Trit Addition simulation (Trit 2 and 3) is taken as example for the proof-of-concept. In this case, the two 'partial' ternary numbers are $\textbf{p} = p_3p_2 = 12 (\widehat{ = }5)$ and $\textbf{q} = q_3q_2 = 21 (\widehat{ = }7)$, and the carry bit from prior Trit c₁ is 0. In the end, the carry of the addition $p_3+q_3+c_2$ will be sent to the next Trit as c₃. With the given logic value of p, q and $c_1 = 0$, $V_{\mathrm{offset},2} = 0.5$ V, $V_{p,2} = 0.1$ V, and $V_{q,2} = 0.05$ V is set for the first pre-sum operation. Leading to $V_{\mathrm{gs2}} = 0.65$ V, which sets the device resistance to TRS. Therefore, $V_{\mathrm{offset,2}}$ has to be 0.15 V lower for the end-sum operation, resulting in $V_{\mathrm{gs2}} = 0.35$ V and $c_2 = 1$ is sent to Trit3. The corresponding read out resistance in the end-sum is switched to HRS ($s_2 = 0$). Meanwhile, with $c_2 = 1$, the pre-sum operation for Trit 3 is performed simultaneously, as shown on the time axis in figure 8(b). During the pre-sum operation of Trit 3, $V_{\mathrm{offset,3}} = V_{\mathrm{offset,3}} = 0.5$ V and $V_{\mathrm{gs3}} = 0.5$ V+0.05 V$(p_3)+0.1$ V$(q_3)+0.05$ V$(\mathrm{carry}_2) = 0.7$ V. $V_{\mathrm{gs3}}$ is larger than $V_{\mathrm{gs2}}$ so that it sets the resistance of the device to a lower value, i.e TRS. Then for the end-sum operation $V_{\mathrm{offset,new,3}}$ has to be lowered by 0.15 V as well, which changes the $V_{gs3}$ to 0.55 V and sets the c₃ to 1. With the new V_gs MRS ($s_3 = 1$) is achieved in the end. Therefore, $\textbf{sum} = c_3s_3s_2 = 110 (\widehat{ = }12)$.

Because an extra Trit is reserving the carry bit of the MSB, 42 devices are required for implementing a 41-Trits addition operation, same as in the RESET direction implementation. All devices share the BL connected to the bottom electrode. For all devices, which are not in the computing states, the gate voltages are set to 0 V to ensure the system functioning properly.

As a representative only the processing signals of 1st, 20th and 41th Trits are shown in figure 8(c). From Trit₁₉ it can be recognized that the gate-source voltage drop is set to 0 V out of working time to prevent the drift current flowing into the device. When it is set to TRS in the first set step, the device will be programmed with a new V_gs in the end-sum operation. The two read out resistances are clearly different while the ones of the 41th Trit are at the same level. By different read out resistances the carry bit is always set to 1 and the offset voltage is lowered by 0.15 V.

The ternary Ł₃ logic in its functionally complete form consists of three basic operations, namely negation, implication and false operation. The negation and implication operation each consist of a initialization step into the LRS/HRS for the RESET/SET direction logic, then an logic step and finally a read out step. The read out step is technically not needed to successfully perform the logic operation and has only been included in the previous sections to show the correctness of the logic operations. The false operation consists of writing the cell into the highest/lowest resistive state for the RESET/SET logic. All logical operations in SET and RESET direction operate on a single cell per Trit.

The ternary adder concepts for the RESET and SET direction operate on a single cell at each bit position plus an additional cell to store the carry output of the last bit position. The n-bit adder then requires n+1 devices to operate for both directions. In both switching direction, the device at position n is first initialized. Depending on the carry output of the previous stage the offset voltage is chosen. Thereafter, the logic step is performed and the device state is read out, to assess whether it belongs to the three valid resistance states (R₀, R₁ or R₂ for the RESET direction and HRS, MRS and LRS for the SET direction). If it does, the addition is finished, otherwise the offset is modified and the device is initialized, programmed and read out again. Therefore, for the calculation of each bit of the addition, either one initialization, one programming and one read step are required or two of each. As for the logic computation, the second read out step is only included to verify the correctness.

The programming energies for the various operations are extracted from the simulations using

$\begin{equation} E = \int_{t_1}^{t_2}I_{\mathrm{cell}}\left(t\right)\cdot V_{\mathrm{applied}}\left(t\right) \, \textrm{dt}, \end{equation} \tag{ 13 }$

where t₁ and t₂ indicate the beginning and end of the voltage pulse. All relevant energy components are shown in table 8 for the RESET direction and in table 9 for the SET direction. For the RESET direction logic operations, only the LRS, R₀, and R₁ are required. The logic operations are evaluated based on simulation results from 1 R line array structures, as in the experimental study in [28]. For the adder, the results are based on 1S1R simulations as the selectors are required to enable the adder in crossbar arrays. If multiple values are given, the first value refers to the 1 R simulations and the second value refers to the 1S1R simulations. For the original adder concept six HRS and one LRS were required to be differentiated. This requirement was simplified here to only require the differentiation of three HRS states and one LRS state. Still, depending on the RESET voltage all six HRS levels can be accessed. Therefore, table 8 is extended to include all possible HRS states. The initialization step costs the most energy. Due to the higher initial current flow at lower resistances, starting from a smaller resistance and programming into the LRS is more expensive. The higher energy consumption with selector results from the higher programming voltages which are roughly larger by a factor of two. This is due to the fact that if the devices are in the LRS, a large voltage will drop across the selector resulting in a very low ohmic selector. Programming from the LRS consumes more energy if the HRS state towards which we program is smaller, due to the higher currents. For the readout step the energy consumption is higher the smaller the resistances are. The readout consumes significantly more energy if the 1S1R structure is used, as the read voltage is much higher (−1.7 V instead of −0.1 V).

The results for the SET direction scheme are obtained in the same fashion. Generally, the energy cost is smaller due to the higher resistances programmed through the multilevel SET. Here, all results are obtained from simulations in the 1T1R configuration. From these results, the best and worst cases energy consumption can be determined. For a logic operation in the RESET direction in the 1S1R array the worst/best case energy costs are 2.425 nJ/2.114 nJ. They are obtained, when the cell is in the LRS/R₁ initially and is programmed to the LRS/R₁. The corresponding values for the SET direction are 98 pJ/86.5 pJ, obtained for the initial device being in the TRS/HRS and being programmed into the LRS/HRS.

The addition algorithm requires in the best case one SET, one RESET and one read operation per Bit position. In the worst case it requires 2 SET, 2 RESET and one read operation per Bit position. For the last Bit position an additional SET and RESET is required, to program the final sum bit corresponding to the carry Bit from the second to last stage. The number of operations is the same for the SET and RESET direction mapping approaches, only the sequence of SET and RESET is switched. The corresponding worst case energy per Bit for the RESET direction is 4.252 pJ. This is obtained, when the cell is initially in the LRS, is then programmed into R₃ and read out. The readout of R₃ requires another initialization (from R₃) and a subsequent programming into R₀. The best case energy is obtained, if the device is initialised into the LRS starting from R₅, then programmed into R₂ and finally readout, resulting in a best case energy of 1.85 nJ. For the SET direction adder the worst case and best case energies for the addition are 659 pJ and 77.5 pJ. The worst case energy is obtained, if the device is initially in the TRS3 and subsequently programmed into the TRS3 and read out. This requires an additional initialization from the TRS3 with a programming into the LRS and a read out. In the best case situation, the device is initially in the HRS, programmed into the HRS and then read out.