Digital video cassette (DVC) is a quickly proliferating new standard for real-time digital video ... more Digital video cassette (DVC) is a quickly proliferating new standard for real-time digital video recording. DVC is presently used both in consumer and professional applications. In this paper we describe the DVC principles, data organization and video decoding algorithm. Although typically DVC video has very good quality, at low-light levels noise becomes pronounced. We show that noise in the DVC can be reduced by digital postfiltering. For this purpose, a wavelet denoising algorithm is suggested due to its unique properties. Wavelet denoising is described in detail and results of noise reduction are illustrated on examples
In deep-submicron technology interconnects started to be a serious limiting factor for high-perfo... more In deep-submicron technology interconnects started to be a serious limiting factor for high-performance design. In order to design high performance or low-power system-on-a-chip (SOC), it is mandatory to effectively address the impact of wires on propagation delay and power consumption. This can only be achieved if the interconnect is properly modeled. This paper presents a comprehensive study of the impact
In this paper we propose an efficient technique for energy savings in DSM technology. The core of... more In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeater insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeater insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 ÎĽm, 2.5 V, 6-metal-layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5 V down to 1.5 K
... In order to evaluate the power-saving capabilities of our algorithm, we have simulated five d... more ... In order to evaluate the power-saving capabilities of our algorithm, we have simulated five different DFGs (dia-grams are shown in Figure 5) using HSPICE. ... Con$ on Qual. Elec. Design, 2000, 137-293. [2] L. Anghel, M. Nicolaidis, I. Alzaher-Noufal, Self-checking circuits versus ...
Abstract This paper elaborates a macroscopic, non-iterative algorithm to estimate the fuel consum... more Abstract This paper elaborates a macroscopic, non-iterative algorithm to estimate the fuel consumption of vehicles. The algorithm uses the Willan's internal combustion engine model and needs no instantaneous values of speed and acceleration.
IEEE Transactions on Very Large Scale Integration Systems, 2004
... [8] K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimot... more ... [8] K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insen-sitive current sense ... Imed Ben Dhaou and Hannu Tenhunen ...
IEEE Transactions on Circuits and Systems I-regular Papers, 2003
Abstract This paper reports an analogy between on-chip signaling and digital communication over a... more Abstract This paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The ...
With the increasing demands for battery operated system, low-power VLSI design became an active r... more With the increasing demands for battery operated system, low-power VLSI design became an active research within the circuit design community [1]. The aim is to investigate design methodologies for lowpower integrated circuits (ICs). Current ICs are made using CMOS ...
This paper describes a method for reducing the interconnection peak current in a system-on-chip d... more This paper describes a method for reducing the interconnection peak current in a system-on-chip design. The method is applied to a globally asynchronous locally synchronous 128-point wavelet processor array design with 1.45 million equivalent gates. In the proposed approach, data transfer along buffered highly capacitive on-chip interconnects is realized using asynchronous communication channels. These channels are managed by a global self-timed controller which allows only one channel to be active at a time. This method reduces the interconnect peak current by 75% compared to a design where wires are driven synchronously. This approach allows the reduction of the area devoted to the decoupling capacitance needed to suppress power supply noise.
This paper proposes a client-server network architecture for safe pilgrimage in the kingdom of Sa... more This paper proposes a client-server network architecture for safe pilgrimage in the kingdom of Saudi Arabia. The proposed architecture allows for continuous tracking and trip planning of shuttle-bus during its journey to the holy city of Makkah using assisted GPS. For personnel identification the architecture supports RFID technology. The proposed RFID technology is Java contactless card that enables both bus drivers and travel agencies to prevent unauthorized passengers to board the bus and to supervise authorized passengers during breaks. Furthermore Java card based system facilitates offline and online passengers identifications at the various checking points by the Saudi authorities. Wireless access to the internet is a vital layer in the proposed architecture as it allows for tracking, trip planning and on-line identity verification. Experimental results for wireless access to the internet show that HSPA is better than WiMAX as it offers acceptable quality of service at vehicle speed that exceeds 120kmph.
ABSTRACT A fault detection method is proposed for a class of nonlin-ear filters, namely stack fil... more ABSTRACT A fault detection method is proposed for a class of nonlin-ear filters, namely stack filters. The core of the method is the sample selection probability vectors of stack filters. A simple implementation for fault diagnosis is derived based on this notion.
Digital video cassette (DVC) is a quickly proliferating new standard for real-time digital video ... more Digital video cassette (DVC) is a quickly proliferating new standard for real-time digital video recording. DVC is presently used both in consumer and professional applications. In this paper we describe the DVC principles, data organization and video decoding algorithm. Although typically DVC video has very good quality, at low-light levels noise becomes pronounced. We show that noise in the DVC can be reduced by digital postfiltering. For this purpose, a wavelet denoising algorithm is suggested due to its unique properties. Wavelet denoising is described in detail and results of noise reduction are illustrated on examples
In deep-submicron technology interconnects started to be a serious limiting factor for high-perfo... more In deep-submicron technology interconnects started to be a serious limiting factor for high-performance design. In order to design high performance or low-power system-on-a-chip (SOC), it is mandatory to effectively address the impact of wires on propagation delay and power consumption. This can only be achieved if the interconnect is properly modeled. This paper presents a comprehensive study of the impact
In this paper we propose an efficient technique for energy savings in DSM technology. The core of... more In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeater insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeater insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 ÎĽm, 2.5 V, 6-metal-layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5 V down to 1.5 K
... In order to evaluate the power-saving capabilities of our algorithm, we have simulated five d... more ... In order to evaluate the power-saving capabilities of our algorithm, we have simulated five different DFGs (dia-grams are shown in Figure 5) using HSPICE. ... Con$ on Qual. Elec. Design, 2000, 137-293. [2] L. Anghel, M. Nicolaidis, I. Alzaher-Noufal, Self-checking circuits versus ...
Abstract This paper elaborates a macroscopic, non-iterative algorithm to estimate the fuel consum... more Abstract This paper elaborates a macroscopic, non-iterative algorithm to estimate the fuel consumption of vehicles. The algorithm uses the Willan's internal combustion engine model and needs no instantaneous values of speed and acceleration.
IEEE Transactions on Very Large Scale Integration Systems, 2004
... [8] K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimot... more ... [8] K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insen-sitive current sense ... Imed Ben Dhaou and Hannu Tenhunen ...
IEEE Transactions on Circuits and Systems I-regular Papers, 2003
Abstract This paper reports an analogy between on-chip signaling and digital communication over a... more Abstract This paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The ...
With the increasing demands for battery operated system, low-power VLSI design became an active r... more With the increasing demands for battery operated system, low-power VLSI design became an active research within the circuit design community [1]. The aim is to investigate design methodologies for lowpower integrated circuits (ICs). Current ICs are made using CMOS ...
This paper describes a method for reducing the interconnection peak current in a system-on-chip d... more This paper describes a method for reducing the interconnection peak current in a system-on-chip design. The method is applied to a globally asynchronous locally synchronous 128-point wavelet processor array design with 1.45 million equivalent gates. In the proposed approach, data transfer along buffered highly capacitive on-chip interconnects is realized using asynchronous communication channels. These channels are managed by a global self-timed controller which allows only one channel to be active at a time. This method reduces the interconnect peak current by 75% compared to a design where wires are driven synchronously. This approach allows the reduction of the area devoted to the decoupling capacitance needed to suppress power supply noise.
This paper proposes a client-server network architecture for safe pilgrimage in the kingdom of Sa... more This paper proposes a client-server network architecture for safe pilgrimage in the kingdom of Saudi Arabia. The proposed architecture allows for continuous tracking and trip planning of shuttle-bus during its journey to the holy city of Makkah using assisted GPS. For personnel identification the architecture supports RFID technology. The proposed RFID technology is Java contactless card that enables both bus drivers and travel agencies to prevent unauthorized passengers to board the bus and to supervise authorized passengers during breaks. Furthermore Java card based system facilitates offline and online passengers identifications at the various checking points by the Saudi authorities. Wireless access to the internet is a vital layer in the proposed architecture as it allows for tracking, trip planning and on-line identity verification. Experimental results for wireless access to the internet show that HSPA is better than WiMAX as it offers acceptable quality of service at vehicle speed that exceeds 120kmph.
ABSTRACT A fault detection method is proposed for a class of nonlin-ear filters, namely stack fil... more ABSTRACT A fault detection method is proposed for a class of nonlin-ear filters, namely stack filters. The core of the method is the sample selection probability vectors of stack filters. A simple implementation for fault diagnosis is derived based on this notion.
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